IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 13

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 1: Introduction
Reset Controller
\
Figure 1–4. Reset Sequence
Figure 1–5. Block Diagram of the Reset Sequence Controller
December 2010 Altera Corporation
phy_mgmt_clk_reset
rx_islocked_toref
powerdown_all
rx_is_lockedtodata
phy_mgmt_clk
Transceiver PHY
Avalon-MM
Interface
pll_islocked
rx_oc_busy
tx_ready
rx_ready
f
PHY Management
S
Receiver
Avalon - MM
PCS
3. Finally, rx_ready is asserted and phy_mgmt_clk_reset goes low, ending the reset
Figure 1–5
Stratix V devices.
For additional timing diagrams illustrating resets for many configurations, refer to
Reset Control and Power Down
Stratix IV devices or
Handbook for Stratix V devices.
state.
rx_digitalreset
tx_digitalreset
M
shows the hardware modules and internal signals that implement reset in
Transmitter
PCS
PCS and PMA Control
and Status Register
Reset Controller
Memory Map
rx_analogreset
Reset Control and Power Down
S
Receiver
in volume 4 of the Stratix IV Device Handbook for
PMA
CDR
tx_pll_is_locked
S
Reconfiguration
Dynamic
Transmitter
Transmitter
PMA
PLL
pll_powerdown
in volume 2 of the Stratix V Device
Altera Transceiver PHY IP Core User Guide
phy_mgmt_clk_reset
tx_ready
rx_ready
user logic
to / from
1–7