IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 40

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–6
Figure 4–4. XAUI Top-Level Signals–Hard IP PCS and PMA
Note to
(1)
Altera Transceiver PHY IP Core User Guide
reconfig_fromgxb[67:17] is terminated to ground internally.
Figure
Avalon-MM PHY
SDR Rx XGMII
Clock
Reset
SDR Tx XGMII
Management
and
SDR XGMII TX Interface
Interface
4–3:
f
Optional
Resets
Figure 4–4
implementation which is available for Arria II GX, Cyclone IV GX, and Stratix IV GX
devices.
The following sections describe the signals in each interface.
The XAUI PCS interface to the FPGA fabric uses a single data rate (SDR) XGMII
interface. This interface implements a simple version of Avalon-ST protocol. The
interface does not include ready or valid signals; consequently, the sources always
drive data and the sinks must always be ready to receive data.
For more information about the Avalon-ST protocol, including timing diagrams, refer
to the
Avalon Interface
xgmii_tx_dc[71:0]
xgmii_tx_clk
xmii_rx_dc[71:0]
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
rx_analogreset
rx_digitalreset
tx_digitalreset
illustrates the top-level signals of the XAUI PHY IP core for the hard IP
XAUI Top-Level Signals Hard IP Implementation
Specifications.
Note (1)
rx_phase_comp_fifo_error[3:0]
tx_phase_comp_fifo_error[3:0]
rx_rmfifodatainserted[7:0]
rx_rmfifodatadeleted[7:0]
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
rx_is_lockedtodata[3:0]
reconfig_fromgxb[67:0]
rx_channelaligned[3:0]
rx_set_locktodata[3:0]
rx_is_lockedtoref[3”0]
rx_patterndetect[7:0]
rx_set_locktoref[3:0]
cal_blk_powerdown
rx_seriallpbken[3:0]
rx_rmfifoempty[3:0]
rx_runningdisp[7:0]
reconfig_togxb[3:0]
rx_syncstatus[7:0]
rx_invpolarity[3:0]
tx_invpolarity[3:0]
rx_errdetect[7:0]
gxb_powerdown
rx_rmfifofull[3:0]
pll_powerdown
rx_disperr[7:0]
pll_locked
pll_locked
rx_rlv[3:0]
rx_ready
tx_ready
December 2010 Altera Corporation
Transceiver
Serial Data
Optional
Chapter 4: XAUI PHY IP Core
Reconfiguration
All Optional
Rx and Tx
Transceiver
Status
Controller
Channel
PMA
Interfaces