IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 61

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Interlaken PHY IP Core
Simulation Testbench
Table 5–10. Serial Interface
Simulation Testbench
Table 5–11. Generated Files
December 2010 Altera Corporation
tx_coreclkin
rx_coreclkin
File Name
<project_dir>
<project_dir>/<design_name>/
<design_name>.v or .vhd
<design_name>.qip
<design_name>.bsf
Optional Clocks for Deskew
Signal Name
Table 5–10
When you generate your Interlaken PHY IP core, the Quartus II software generates
the HDL files that define your parameterized IP core. In addition, the Quartus II
software generates an example Tcl script to compile and simulate your design in
ModelSim.
Figure 5–3. Directory Structure for Generated Files
Table 5–11
PHY IP core and the simulation environment which are in clear text.
describes the key files and directories for the parameterized Interlaken
describes the optional clocks that you can create to reduce clock skew.
Figure 5–3
Input
Input
Direction
Description
The top-level project directory.
The top-level design file.
A list of all files necessary for Quartus II compilation.
A Block Symbol File (.bsf) for your Interlaken PHY.
The directory that stores the HDL files that define the Interlaken PHY IP core.
These files are used for synthesis.
<project_dir>
<design_name>.v or .vhd - the parameterized Interlaken PHY IP core
<design_name>.qip - lists all files used in the Interlaken PHY IP design
<design_name>.bsf - a block symbol file for you Interlaken PHY IP core
illustrates the directory structure for the generated files.
<project_dir>/<design_name> - includes PHY IP Verilog and
System Verilog design files for synthesis
<design_name>_sim/alt_interlaken_pcs = includes plain text
Verilog and System Verilog design files for simulation
modelsim_example_script.tcl = example file for compilation and
<design_name>_sim/alt_interlaken_pcs/mentor = PHY IP encrypted
Verilog and System Verilog design files for simulation in ModelSim
when using a VHDL-only license
simulation of the Interlaken PHY IP core
When enabled tx_coreclkin is available as input port which drives
the write side of TX FIFO. Altera recommends using this clock to
reduce clock skew. When disabled, tx_cllkout drives the write side
the TX FIFO.
When enabled rx_coreclkin is available as input port which drives
the read side of RX FIFO. Altera recommends using this clock to
reduce clock skew. When disabled, rx_cllkout drives the write side
the RX FIFO.
Description
Altera Transceiver PHY IP Core User Guide
5–9