IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 38

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–4
Configurations
Figure 4–2. XAUI PHY Using One Channel Low Latency PHY Controller
Altera Transceiver PHY IP Core User Guide
To MAC
72 bits @ 156.25 Mbps
Interconnect
SDR XGMII
System
Fabric
For a description of the PMA analog options, refer to
page
Figure 4–2
if your variant includes a single instantiation of the XAUI IP core, the transceiver
reconfiguration control logic is included in the XAUI PHY IP core.
For more information about transceiver reconfiguration, refer to
Transceiver Reconfiguration
8–4.
illustrates one configuration of the XAUI IP core. As this figure illustrates,
Hard XAUI PHY
Transceiver Quad 0
S
leave
Avalon-MM
Inter-
Mgmt
PHY
Interconnect
System
Fabric
M
Controller.
PCS
S
S
S
S
Reconfiguration
Low Latency
PMA Channel
Alt_PMA
Controller
Transceiver
Controller
Controller
“PMA Analog Options” on
December 2010 Altera Corporation
Chapter 4: XAUI PHY IP Core
Chapter 9,
4
4
4 x 3.125 Gbps serial
Configurations