IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 114

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

10–8
Custom PHY
Table 10–5. Comparison of ALTGX Megafunction and Custom PHY Parameters
Altera Transceiver PHY IP Core User Guide
What is the number of channel?
Which subprotocol will you be using? (×4, ×8)
What is the channel width?
What is the effective data rate?
What is the input clock frequency?
tx/rx_8b_10b_mode
What is the deserializer block width?
Single
Double
Use manual word alignment mode
Use manual bitslipping mode
Use the built-in ‘synchronization state machine’
Enable run length violation checking with a run length of
What is the word alignment pattern
What is the word alignment pattern length
What is the 20-bit rate match pattern1
(usually used for +ve disparity pattern)
What is the 20-bit rate match pattern1
(usually used for -ve disparity pattern)
What is the byte ordering pattern
Note to
(1) This parameter is on the Datapath tab.
Table
Protocol Settings—Rate match/Byte order
Protocol Settings—Rate match/Byte order
Parameter Differences
ALTGX Parameter Name (Default Value)
10–5:
Protocol Settings–Word Aligner
This section lists the differences between the parameters and signals for the Custom
PHY IP core nd the ALTGX megafunction when configured in the Basic functional
mode.
Table 10–5
megafunction parameters.
lists the Custom PHY parameters and the corresponding ALTGX
General
Bonded group size in lanes (1–5)
Deserializer block width:
Auto
Single
Double
Word aligner pattern length
Number of lanes
Serialization factor
Data rate
Input clock frequency
Enable 8B/10B encoder/decoder
Word alignment mode
Run length
Word alignment pattern
Rate match insertion/deletion +ve disparity pattern
Rate match insertion/deletion -ve disparity pattern
Byte ordering pattern
Custom PHY Parameter Name
Chapter 10: Migrating from Stratix IV to Stratix V
Word Aligner
Rate Match
Byte Order
(1)
December 2010 Altera Corporation
Custom PHY