IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 112

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

10–6
Table 10–4. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 2 of 3)
Altera Transceiver PHY IP Core User Guide
pll_powerdown
rx_analogreset
rx_digitalreset
tx_digitalreset
gxb_powerdown
cal_blk_powerdown
tx_datain
tx_ctrlenable
tx_detectrxloop
tx_forcedispcompliance
tx_pipemargin[2:0]
rateswitch[0]
powerdn
rx_elecidleinfersel
rx_dataout
rx_ctrldetect
pipedatavalid
pipe8b10binvpolarity
pipeelecidle
pipephydonestatus
pipestatus
rx_pll_locked
rx_freqlocked
pll_locked
rx_syncstatus
(Note 1)
tx_forceelecidle
txswing
tx_pipedeemph[0]
Stratix IV GX Device Signal Name
Not available
Not available
Refer to the
Interface” on page 6–6
(PIPE) IP Core Registers” on page 6–6
tx_ready (reset control status)
rx_ready (reset curl status)
pipe_txdata
pipe_txdatak
pipe_txdetectrx_loopback
pipe_txcompliance
pipe_txmargin
pipe_rate[1:0]
pipe_powerdown
pipe_eidleinfersel
pipe_rxdata
pipe_rxdatak
pipe_rxvalid
pipe_rxpolarity
pipe_rxelecidle
pipe_phystatus
pipe_rxstatus
rx_is_lockedtoref
rx_is_lockedtodata
pll_locked
rx_syncstatus (also management
interface)
pipe_txelecidle
pipe_txswing
pipe_txdeemph
PIPE interface Ports
Non-PIPE ports
Stratix V Device Signal Name
“Avalon-MM PHY Management
and
“PCI Express PHY
Chapter 10: Migrating from Stratix IV to Stratix V
December 2010 Altera Corporation
1
1
1
1
1
1
1
1
[<n><d>-1:0]
[(<d>/8)*<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[3<n>-1:0]
[<n>-1:0]
[2<n>-1:0]
[3<n>-1:0]
[<n>-*<d>-1:0]
[(<d>/8)*<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[3<n>-1:0]
[<n>--1:0]
[<n>--1:0]
1
[(<d>/8)*<n>-1:0]
PCI Express PHY (PIPE)
Width