IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 31

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: 10GBASE-R PHY IP Core
Interfaces
Figure 3–5. Stratix V Clock Generation and Distribution
Table 3–12. Clock Signals
December 2010 Altera Corporation
pll_ref_clk
Signal Name
1
10GBASE-R Hard IP Transceiver Channel - Stratix V GT
Figure 3–5
To ensure proper functioning of the PCS, the maximum PPM difference between the
pll_ref_clk and xgmii_tx_clk clock inputs is 100 PPM. To meet this specification,
you should use xgmii_rx_clk to drive xgmii_tx_clk. The CDR logic recovers
257.8125 MHz clock from the incoming data.
Table 3–13
TX
RX
xgmii_rx_clk
156.25 MHz
xgmii_tx_clk
illustrates the clock generation and distribution for Stratix V devices.
describes the clock inputs.
Direction
64
64
Input
RX PCS
GPLL
TX PCS
8/33
TX PLL reference clock which must be 644.53725 MHz.
257.8125
MHz
40
40
257.8125
MHz
RX PMA
TX PMA
TX PLL
Description
Gbps serial
Gbps serial
Altera Transceiver PHY IP Core User Guide
10.3125
644.53125 MHz
10.3125
pll_ref_clk
3–13