IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 50

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–16
Table 4–15. Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices (Part 2 of 2)
TimeQuest Timing Constraints
Example 4–1. Synopsys Design Constraints for Clocks
set_time_format -unit ns -decimal_places 3
derive_pll_clocks
derive_clock_uncertainty
#
# input clocks
create_clock -name {xgmii_tx_clk}-period 6.400 -waveform {0.000 3.2} \
create_clock -name {phy_mgmt_clk} -period 20.000 -waveform {0.000 10.0} \
create_clock -name {refclk} -period 6.400 -waveform {0.000 3.2} \
# generated clocks
# xgmii_rx_clk is generated from coreclkout
#****** Use this section for Stratix IV Hard XAUI ******
create_generated_clock -name {xgmii_rx_clk_0} -source [get_pins -compatibility_mode
{*hxaui_0|hxaui_alt4gxb|hxaui_alt4gxb_alt4gxb_dksa_component|central_clk_div0|
coreclkout}]-multiply_by 1 [get_ports {xgmii_rx_clk}]
#****** Use this section for Stratix IV Soft XAUI ******
#create_generated_clock -name {xgmii_rx_clk_0} -source [get_pins -compatibility_mode
{*alt_pma_0|alt_pma_tgx_inst|pma_direct|auto_generated|central_clk_div0|refclkout} ] \
#-multiply_by 1 [get_ports {xgmii_rx_clk}]
Altera Transceiver PHY IP Core User Guide
rx_patterndetect[7:0]
rx_rmfifodatadeleted[7:0]
rx_rmfifodatainserted[7:0]
rx_runningdisp[7:0]
rx_syncstatus[7:0]
rx_phase_comp_fifo_error[3:0]
tx_phase_comp_fifo_error[3:0]
rx_rlv[3:0]
[get_ports {xgmii_tx_clk}]
[ get_ports {phy_mgmt_clk} ]
[ get_ports {pll_ref_clk} ]
Signal Name
Example 4–1
analysis you must decouple the clocks in different time domains.
provides the .sdc timing constraints for the XAUI clocks. To pass timing
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Indicates that the word alignment pattern programmed has been
detected in the current word boundary. The rx_patterndetect
signal is 2 bits wide per channel for a total of 8 bits per XAUI link.
Status flag that is asserted when the rate match block deletes a ||R||
column. The flag is asserted for one clock cycle per deleted ||R||
column.
Status flag that is asserted when the rate match block inserts a ||R||
column. The flag is asserted for one clock cycle per inserted ||R||
column.
Asserted when the current running disparity of the 8B/10B decoded
byte is negative. Low when the current running disparity of the
8B/10B decoded byte is positive.
Synchronization indication. RX synchronization is indicated on the
rx_syncstatus port of each channel. The rx_syncstatus signal
is 2 bits wide per channel for a total of 8 bits per XAUI link.
Indicates a RX phase comp FIFO overflow or underrun condition.
Indicates a TX phase compensation FIFO overflow or underrun
condition.
Asserted if the number of continuous 1s and 0s exceeds the number
that was set in the run-length option. The rx_rlv signal is
asynchronous to the RX datapath and is asserted for a minimum of
2 recovered clock cycles.
Description
December 2010 Altera Corporation
TimeQuest Timing Constraints
Chapter 4: XAUI PHY IP Core