IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 11

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 1: Introduction
Reset Controller
Figure 1–3. Stratix V Device Non-Bonded Mode Clocking
December 2010 Altera Corporation
clock input
Reference
Rx data
Tx data
Rx data
Tx data
pin
In non-bonded mode, separate CGBs are used for each channel and the skew between
channels is not carefully controlled.
The reset controller generates a reset sequence appropriate for the protocol. Using the
reset controller section of the memory map, you can choose have the reset sequence
apply to all channels (the default behavior), or mask out some channels so that those
channels will not be affected by the reset sequence. For bonded modes, you should
allow the reset sequence to affect all channels.
The reset controller drives the following reset signals:
■
■
■
rx_analogreset—This signal resets the analog CDR and deserializer logic present
in the RX channel. (CDR is the first step of the power-up process.)
rx_digitalreset—This signal resets all digital logic in the RX PCS and PMA.
tx_digitalreset—This signal resets all logic in the TX PCS.
Ser = Serializer
DeSer = DeSerializer
Transceiver
Transceiver
PMA
PMA
PMA
PMA
Tx PLL
CDR
CDR
Clock
Data
Ser
Ser
frequency
clock
High
Figure 1–3
DeSer
DeSer
Clock Gen
Clock Gen
Buffer
Buffer
(CGB)
(CGB)
/n, /m
/n, /m
PCS
PCS
illustrates mode for Stratix V devices.
PCS
PCS
Rx PCS
Tx PCS
Rx PCS
Tx PCS
Low speed
Low speed
clock(s)
clock(s)
parallel
parallel
Altera Transceiver PHY IP Core User Guide
FPGA-fabric
interface
1–5