IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 10

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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Altera Transceiver PHY IP Core User Guide
Figure 1–2. Stratix V Device Bonded Mode Clocking
Reference
clock input
Rx data
Rx data
pin
Tx data
Tx data
Ser = Serializer
DeSer = DeSerializer
Channel PLL
Transceiver
PMA
PMA
Tx PLL
CDR
CDR
Clock
Data
Ser
Ser
frequency
clock
High
Clock Gen
Buffer
(CGB)
/n, /m
DeSer
DeSer
Low speed
clock(s)
parallel
PCS
PCS
December 2010 Altera Corporation
Tx PCS
Rx PCS
Tx PCS
Rx PCS
Chapter 1: Introduction
FPGA-fabric
interface
Reset Controller