IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 55

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Interlaken PHY IP Core
Interface
Table 5–3. Parameters
Interface
December 2010 Altera Corporation
Datapath mode
Lane rate
Number of lanes
Metaframe length in
words
Add signals
Create tx_coreclkin
port
Create rx_coreclkin
port
Parameter
1
Figure 5–2
The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used to
define interfaces in the _hw.tcl.
Duplex, RX, TX
3125 Mbps
5000 Mbps
6250 Mbps
6375 Mbps
10312.5 Mbps
1–24
1–8191
On/Off
On/Off
On/Off
illustrates the top-level signals of the Interlaken PHY IP core.
Value
Optional Ports
Specifies the mode of operation as Duplex, RX, or TX mode.
Specifies the link bandwidth. The following table specifies the
frequency of the reference clock you must provide to achieve
these lane rates and the corresponding PCS frequency.
Rate
3125
5000
6250
6375
10312.5
Specifies the number of lanes in a link over which data is striped.
Specifies the number of words in a metaframe. The default value
is 2048.
When you turn this option on, rx_parallel_data[71:69] are
included in the top-level module. These optional signals report the
status of word and synchronization locks and CRC32 errs. Refer
to
When selected tx_coreclkin is available as input port which
drives the write side of TX FIFO, When deselected, an internal state
machine takes control. tx_user_clkout (which is a master
tx_clockout) drives the TX write side of FIFO. tx_user_clkout
is also available as an output port.
When selected rx_coreclkin is available as input port which
drives the read side of RX FIFO, When deselected, an internal state
machine takes control. rx_user_clkout (which is a master
rx_clockout) drives the RX read side of FIFO. rx_user_clkout
is also available as an output port.
Table 5–5 on page 5–5
Ref Clock
156.25
250.0
312.5
318.75
515.625
for more information.
Description
Altera Transceiver PHY IP Core User Guide
5–3