IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 7

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
f
The Altera
protocol-specific PHYs:
■
■
■
■
■
■
The protocol-specific PHYs automatically configure settings for the physical coding
sublayer (PCS) module, leaving a small number of parameters in the physical media
attachment (PMA) module for you to configure. You can use the Custom PHY for
applications that require more flexible settings. The design of all of these PHYs is
modular and uses standard interfaces. All PHYs include an Avalon
Memory-Mapped (Avalon-MM) interface to access control and status registers and an
Avalon Streaming (Avalon-ST) interface to connect to the MAC for data transfer. The
control and status registers store device-dependent information about the PCS and
PMA modules. You can access this device-dependent information using the
device-independent Avalon-MM interface, reducing overall complexity of your
design and the number of device-dependent signals that you must expose in your
top-level module.
For more information about the Avalon-MM and Avalon-ST protocols, including
timing diagrams, refer to the
Table 1–1
devices. Typically, the PCS and PMA are implemented as hard logic, saving FPGA
resources and reducing the complexity of verification. In some cases, the PCS is also
available in soft logic as
Table 1–1. Stratix V GX Support for Protocol Specific PHY IP Cores
10GBASE-R
XAUI
Interlaken
PCI Express Gen1 and Gen2
Custom PHY
Low latency PHY
10GBASE-R PHY IP Core
XAUI PHY IP Core
Interlaken PHY IP Core
PCI Express PHY (PIPE) IP Core
Custom PHY IP Core
Low Latency PHY IP Core
shows hard and soft implementation support for these IP cores in Stratix
®
PHY Protocol
Transceiver PHY IP Core User Guide describes the following
Table 1–1
Avalon Interface
indicates.
Soft PCS
Yes
No
No
No
No
No
Specifications.
Hard PCS
Altera Transceiver PHY IP Core User Guide
Yes
Yes
Yes
Yes
Yes
No
1. Introduction
®
Hard PMA
Yes
Yes
Yes
Yes
Yes
Yes
®
V