IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 88

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–10
Table 7–10. Avalon-ST RX Interface (Part 2 of 2)
Figure 7–5. Custom PHY IP Core
Note to
(1) Blocks in gray are soft logic. Blocks in white are hard logic.
Altera Transceiver PHY IP Core User Guide
rx_runningdisp
rx_enabyteord
Interconnect
System
Figure
Fabric
Avalon-MM PHY Management Interface
Signal Name
7–5:
Rx Data
Tx Data
Clocks
Reset
The Avalon-MM PHY management module includes master and slave interfaces. This
component acts as a bridge. It transfers commands received on its Avalon-MM slave
interface to its Avalon-MM master port. This interface provides access to control and
status information for the PCS, PMA, and Reconfiguration blocks.
Figure 7–5
Custom PHY IP Core
S
Avalon-MM
(Note 1)
Mgmt
PHY
illustrates the role of the PHY Management module in the Custom PHY.
Direction
Interconnect
Source
System
Input
Fabric
M
This status signal indicates the disparity of the incoming data.
This signal is created if you turn On the Enable byte ordering block
control option on the Byte Order tab. A byte ordering operation occurs
whenever rx_enabyteord is asserted. To perform multiple byte
ordering operations, deassert and reassert rx_enabyteord.
S
S
S
Reconfiguration
Controller
Avalon-MM
Avalon-MM
Transceiver
Reset
Controller
Control
Status
Status
Dynamic
Partial
Reconfiguration
Resets
Clocks
Tx Parallel Data
Rx Parallel Data
Description
Control
Custom PHY PCS and PMA
Rx Serial Data & Status
December 2010 Altera Corporation
Chapter 7: Custom PHY IP Core
Tx Serial Data
Interfaces