IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 68

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–4
Table 6–4. Avalon-ST TX Inputs
Table 6–5. Avalon-ST RX Inputs
Altera Transceiver PHY IP Core User Guide
pipe_txdata[<n><d>-1:0]
pipe_txdatak[<n><d>/8-1:0]
pipe_rxdata[<n><d>-1:0]
pipe_rxdatak[<n><d>/8-1:0]
pipe_rxvalid[<n>-1:0]
Avalon-ST TX Input Data from PCI Express PHYMAC
Avalon-ST RX Output Data to PCI Express PHYMAC
Avalon Memory-Mapped (Avalon-MM) PHY Management Interface
Signal Name
Signal Name
f
Table 6–4
driven from the PCI Express PHYMAC to the PCS. This is an Avalon sink interface.
For more information about the Avalon-ST protocol, including timing diagrams, refer
to the
Table 6–5
driven from the PHY (PIPE) to the PHYMAC. This is an Avalon source interface.
The Avalon-MM PHY management block includes master and slave interfaces. This
component acts as a bridge. It transfers commands received on its Avalon-MM slave
interface to its Avalon-MM port. This interface provides access to features of the PCS
and PMA that are not part of the standard PIPE interface.
Avalon Interface
describes the signals in the Avalon-ST input interface. These signals are
describes the signals in the Avalon-ST output interface. These signals are
Source
Source
Source Asserted when RX data and control are valid.
Sink
Sink
Dir
Dir
Specifications.
This is RX parallel data driven from the PHY (PIPE). The ready latency on
this interface is 0, so that the MAC must be able to accept data as soon
as the PHY comes out of reset.
Data and control indicator for the source data. Bit 0 correspond the low
byte of pipe_rxdata. Bit 1 corresponds to the upper byte. When 0,
indicates that pipe_rxdata is data, when 1, indicates that
pipe_rxdata is control.
This is TX parallel data driven from the PCI Express PHYMAC. The ready
latency on this interface is 0, so that the PHY must be able to accept data
as soon as the PHY comes out of reset.
Data and control indicator for the received data. When 0, indicates that
pipe_txdata is data, when 1, indicates that pipe_txdata is control.
Description
Description
Chapter 6: PCI Express PHY (PIPE) IP Core
December 2010 Altera Corporation
Interfaces