IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 19

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Figure 3–1. Complete 10GBASE-R PHY Design
December 2010 Altera Corporation
To MAC
To MAC
To Embedded
Controller
72 bits @ 156.25 Mbps
72 bits @ 156.25 Mbps
The Altera 10GBASE-R PHY IP core implements the functionality described in
802.3 Clause
optical fiber at a line rate of 10.3125 Gbps. In a multi-channel implementation of
10GBASE-R, each channel of the 10GBASE-R PHY IP core operates independently.
You can instantiate multiple channels to achieve higher bandwidths. The PCS is
available in soft logic for Stratix IV GT devices; it connects to a separately instantiated
hard PMA.
Figure 3–1
In this configuration, 10GBASE-R PHY IP core includes a soft PCS and a hard PMA.
The soft PCS connects to an Ethernet MAC running at 156.25 Mbps and transmits data
to a hard 10 Gbps transceiver PMA running at 10.3125 Gbps in a Stratix IV GT device.
SDR XGMII
SDR XGMII
S
illustrates a multiple 10 GbE channel IP core in a Stratix IV GT device.
Management
49. It delivers serialized data to an optical module that drives multi-mode
Avalon-MM
Bridge
PHY
10GBase-R PHY
connections
Avalon-MM
ALTGX<0>
ALTGX<n>
M
10GBASE-R
10GBASE-R
(64b/66b)
(64b/66b)
S
PCS
PCS
S
S
S
Low Latency
Transceiver
Controller
Controller
Reconfig
10GBASE-R
10GBASE-R
10.3 Gbps
10.3 Gbps
Alt_PMA
S
Alt_PMA
S
3. 10GBASE-R PHY IP Core
Altera Transceiver PHY IP Core User Guide
10.3125 Gbps serial
10.3125 Gbps serial
To HSSI Pins
To HSSI Pins
IEEE