IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 9

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 1: Introduction
PCS
PCS
PMA
Reset Controller
December 2010 Altera Corporation
The following sections provide a brief introduction to each of the modules illustrated
in
The PCS implements part of the physical layer specification for networking protocols.
Depending upon the protocol that you choose, the PCS may include many different
functions. Some of the most commonly included functions are: 8B/10B, 64b/66b, or
64b/67b encoding and decoding, rate matching and clock compensation, scrambling
and de-scrambling, word alignment, phase compensation, error monitoring, and
gearbox.
The PMA receives and transmits differential serial data on the device external pins.
The transmit (TX) channel supports programmable pre-emphasis and programmable
output differential voltage (V
data.The RX channel supports offset cancellation to correct for process variation and
programmable equalization. It converts serial data to parallel data for processing in
the PCS. The PMA also includes a clock data recovery (CDR) module with separate
CDR logic for each RX channel.
The reset controller manages signals to reset and power down the PHY channels and
PLLs. The PHY channels operate in two modes: bonded and non-bonded. In bonded
mode, a single Clock Generation Buffer (CGB) divides the output it receives from the
TX PLL to create the parallel clock inputs the TX channel PMA and PCS modules. The
parallel clocks for each channel are carefully tuned to keep the clock skew below 150
ps.
Figure
Figure 1–2
1–1.
illustrates bonded mode for Stratix V devices.
OD
). It converts parallel input data streams to serial
Altera Transceiver PHY IP Core User Guide
1–3