IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 17

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
December 2010 Altera Corporation
3. To select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in
4. Specify the parameters on the Parameter Settings pages. For detailed explanations
5. If the IP core provides a simulation model, specify appropriate options in the
6. If the parameter editor includes EDA and Summary tabs, follow these steps:
7. Click the Finish button, the parameter editor generates the top-level HDL code for
the MegaWizard Plug-In Manager.
of these parameters, refer to the “Parameter Settings” chapter in this document.
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wizard to generate a simulation model.
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f
c
a. Some third-party synthesis tools can use a netlist that contains the structure of
b. On the Summary tab, if available, select the files you want to generate. A gray
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your IP core, and a simulation directory which includes files for simulation.
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an IP core but no detailed logic to optimize timing and performance of the
design containing it. To use this feature if your synthesis tool and IP core
support it, turn on Generate netlist.
checkmark indicates a file that is automatically generated. All other files are
optional.
Some IP cores provide preset parameters for specific applications. If you
wish to use preset parameters, click the arrow to expand the Presets list,
select the desired preset, and then click Apply. To modify preset settings, in
a text editor edit the <installation directory>\ip\altera\uniphy\lib\<IP
core>.qprs file.
Altera IP supports a variety of simulation models, including
simulation-specific IP functional simulation models and encrypted RTL
models, and plain text RTL models. These are all cycle-accurate models. The
models allow for fast functional simulation of your IP core instance using
industry-standard VHDL or Verilog HDL simulators. For some cores, only
the plain text RTL model is generated, and you can simulate that model.
For more information about functional simulation models for Altera IP
cores, refer to
Handbook.
Use the simulation models only for simulation and not for synthesis or any
other purposes. Using these models for synthesis creates a nonfunctional
design.
If file selection is supported for your IP core, after you generate the core, a
generation report (<variation name>.html) appears in your project directory.
This file contains information about the generated files.
The Finish button may be unavailable until all parameterization errors
listed in the messages window are corrected.
Simulating Altera Designs
in volume 3 of the Quartus II
Altera Transceiver PHY IP Core User Guide
2–3