IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 101

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 8: Low Latency PHY IP Core
Interfaces
Table 8–6. Avalon-MM PHY Management Interface
Table 8–7. PMA Channel Control and Status
December 2010 Altera Corporation
phy_mgmt_clk
phy_mgmt_reset
phy_mgmtaddress[8:0]
phy_mgmtwritedata[31:0]
phy_mgmtreaddata[31:0]
phy_mgmtwrite
phy_mgmtread
0x063
0x064
0x065
0x066
0x067
Offset
Byte
Avalon-MM PHY Management Interface
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
Bits
Signal Name
You can use the Avalon-MM PHY Management interface to read and write registers
that control the TX and RX channels, the PMA powerdown and PLL registers, and
loopback modes.
Register Descriptions
Table 8–7
Interface using word addresses and a 32-bit embedded processor.
R/W
RW
RW
R
R
R
pma_rx_signaldetect
pma_rx_set_locktodata
pma_rx_set_locktoref
pma_rx_is_lockedtodata
pma_rx_is_lockedtoref
describes the registers that you can access over the PHY Management
Register Name
Table 8–6
Direction
Output
Input
Input
Input
Input
Input
Input
describes the signals in this interface.
This clock signal that controls the Avalon-MM PHY management,
calibration, and reconfiguration interfaces. For Stratix IV devices,
the maximum frequency is 50 MHz. For Stratix V devices, the
maximum frequency is 150 MHz.
Global reset signal. A positive edge on this signal triggers a reset.
9-bit Avalon-MM address.
Input data.
Output data.
Write signal.
Read signal.
When channel <n> =1, indicates that receive circuit for
channel <n> senses the specified voltage exists at the
RX input buffer. This option is only operational for the
PCI Express PHY IP core.
When set, programs the RX CDR PLL to lock to the
incoming data. Bit <n> corresponds to channel <n>.
When set, programs the RX CDR PLL to lock to the
reference clock. Bit <n> corresponds to channel <n>.
When asserted, indicates that the RX CDR PLL is
locked to the RX data, and that the RX CDR has
changed from LTR to LTD mode. Bit <n> corresponds
to channel <n>.
When asserted, indicates that the RX CDR PLL is
locked to the reference clock. Bit <n> corresponds to
channel <n>.
Description
Altera Transceiver PHY IP Core User Guide
Description
8–7