IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 81

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Custom PHY IP Core
Parameter Settings
Table 7–2. General Options (Part 2 of 2)
Figure 7–2. Custom PHY with Avalon Interfaces Enabled
December 2010 Altera Corporation
Create rx_coreclkin port
Create tx_coreclkin port
Create optional port
Avalon data interfaces
Name
Figure 7–2
On/Off
On/Off
On/Off
On/Off
shows the top-level interfaces when you enable Avalon data interfaces.
Value
This is an optional clock to drive the coreclk of the RX PCS
This is an optional clock to drive the coreclk of the TX PCS
When you turn this option on, the following signals are added to the
top level of your transceiver for each lane:
■
■
■
■
■
■
■
When you turn this option on, there is a separate Avalon-ST bus for
each lane which includes the control and status signals for that lane.
Layout and transmission of data is big endian. Refer to
This option must be on to use the Transceiver Toolkit.
When you turn this option off, the TX and RX interfaces are
configured as a single data and control bus, regardless of the
number of lanes. The layout and transmission of the TX and RX
buses is little endian. Refer to
rx_syncstatus<n>
rx_is_lockedtoref<n>
rx_is_locedtodata<n>
tx_forceelecidle
rx_is_lockedtoref
rx_is_lockedtodata
rx_signaldetect
Description
Figure
Altera Transceiver PHY IP Core User Guide
7–3.
Figure
7–2.
7–3