IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 62

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–10
Table 5–11. Generated Files
Altera Transceiver PHY IP Core User Guide
File Name
<project_dir>/<design_name>_sim/
alt_interlaken_pcs/
alt_interlaken_pcs_top.v
altera_wait_generate.v
alt_interlaken_pcs_sv.v
amm_slave.v
alt_reset_ctrl_tgx_cdrauto.sv
modelsim_example_script.tcl
f
Both the Verilog and VHDL Interlaken PHY IP have been tested extensively with the
following simulators:
■
■
■
If you select VHDL for Interlaken PHY, only the wrapper generated by the Quartus II
software is in VHDL. All the underlying files are written Verilog or System Verilog. To
enable simulation using a VHDL-only ModelSim license, the underlying Verilog and
System Verilog files for the Interlaken PHY are encrypted so that they can be used
with the top-level VHDL wrapper without purchasing a mixed-language simulator.
For more information about simulating with ModelSim, refer to the
ModelSim Support
ModelSim SE
Synopsys VCS MX
Cadence NCSim
Description
The top-level static Verilog HDL file for the Interlaken PHY IP core. It includes
parameterized port widths.
Generates waitrequest for alt_interlaken_pcs.
The transceiver core and memory-mapped logic for specified number of lanes for
PMA and PLLs.
The Avalon-MM slave logic.
The reset controller logic.
The simulation directory.
The example Tcl script to compile and simulate the parameterized Interlaken PHY
IP core. You must edit this script to include the following information:
■
■
■
These variables are illustrated in
The simulation language
The top-level Interlaken variation name
The name of your testbench
chapter in volume 3 of the Quartus II Handbook.
Example 5–1
December 2010 Altera Corporation
Chapter 5: Interlaken PHY IP Core
Mentor Graphics
Simulation Testbench