IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 48

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–14
Table 4–13. Low Latency PHY Controller
Table 4–14. Optional Control and Status Signals—Soft IP Implementation, Stratix IV GX and Stratix V Devices
Altera Transceiver PHY IP Core User Guide
cal_blk_powerdown
gxb_powerdown
pll_powerdown
pll_locked
rx_ready
tx_ready
rx_channelaligned
rx_disperr[7:0]
rx_errdetect[7:0]
rx_syncstatus[7:0]
PMA Channel Controller
PMA Control and Status Interface Signals–Soft IP Implementation
(Optional)
Signal Name
Signal Name
Table 4–13
Table 4–14
implementation. You can also access the state of these signals using the Avalon-MM
PHY Management interface to read the control and status registers which are detailed
in
instantaneous value of a signal to ensure correct functioning of the XAUI PHY. In such
cases, you can include the required signal in the top-level module of your XAUI PHY
IP core.
Table 4–9 on page
describes the signals in this interface.
lists the optional PMA control and status signals available in the soft IP
Direction
Direction
Output
Output
Output
Input
Input
Input
Output
Output
Output
Output
4–8. However, in some cases, you may need to know the
Powers down the calibration block. A high-to-low transition on this
signal restarts calibration. Only available in Arria II GX and
Stratix IV GX, and Stratix IV GT devices.
When asserted, powers down the entire transceiver block. Only
available in Arria II GX and Stratix IV GX, and Stratix IV GT devices.
Powers down the CMU PLL. Only available in Arria II GX and
Stratix IV GX, and Stratix IV GT devices.
Indicates CMU PLL is locked. Only available in Arria II GX and
Stratix IV GX, and Stratix IV GT devices.
Indicates PMA RX has exited the reset state.
Indicates PMA TX has exited the reset state.
When asserted, indicates that all 4 RX channels are aligned.
Received 10-bit code or data group has a disparity error. It is paired
with rx_errdetect which is also asserted when a disparity error
occurs. The rx_disperr signal is 2 bits wide per channel for a total
of 8 bits per XAUI link.
When asserted, indicates an 8B/10B code group violation. It is
asserted if the received 10-bit code group has a code violation or
disparity error. It is used along with the rx_disperr signal to
differentiate between a code violation error, a disparity error, or
both.The rx_errdetect signal is 2 bits wide per channel for a total
of 8 bits per XAUI link.
Synchronization indication. RX synchronization is indicated on the
rx_syncstatus port of each channel. The rx_syncstatus signal
is 2 bits wide per channel for a total of 8 bits per XAUI link.
Description
Description
December 2010 Altera Corporation
Chapter 4: XAUI PHY IP Core
Interfaces