IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 25

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: 10GBASE-R PHY IP Core
Interfaces
Table 3–6. Mapping from XGMII TX Bus to XGMII SDR Bus (Part 2 of 2)
Table 3–7. SDR XGMII RX Inputs
Table 3–8. Mapping from XGMII RX Bus to the XGMII SDR Bus (Part 1 of 2)
December 2010 Altera Corporation
xgmii_tx_dc[53]
xgmii_tx_dc[61:54]
xgmii_tx_dc[62]
xgmii_tx_dc[70:63]
xgmii_tx_dc[71]
xgmii_rx_dc<n>[71:0]
rx_ready
xgmii_rx_clk
Note to
(1) <n> is the channel number
xgmii_rx_dc[7:0]
xgmii_rx_dc[8]
xgmii_rx_dc[16:9]
Signal Name
Table
SDR XGMII RX Interface
3–7:
Signal Name
Signal Name
Table 3–7
source interface. These signals are driven from the PCS to the MAC.
Table 3–8
interface.
Direction
Source
Output
Input
describes the signals in the SDR XGMII RX interface. This is an Avalon-ST
provides the mapping from the XGMII RX interface to the XGMII SDR
(Note 1)
xgmii_sdr_ctrl[5]
xgmii_sdr_data[55:48]
xgmii_sdr_ctrl[6]
xgmii_sdr_data[63:56]
xgmii_sdr_ctrl[7]
xgmii_sdr_data[7:0]
xgmii_sdr_ctrl[0]
xgmii_sdr_data[15:8]
Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of
data and 1 bit of control.
■
■
■
■
■
■
■
■
Refer to
xgmii_sdr_data and xgmii_sdr_ctrl signals.
Asserted when the RX channel is ready to receive data. Because the
readyLatency on this Avalon-ST interface is 0, the PCS may drive
xgmii_rx_dc_valid as soon as rx_ready is asserted.
This clock is generated by the same reference clock that is used to generate the
transceiver clock. Its frequency is 156.25 MHz. Use this clock for the MAC
interface to minimize the size of the FIFO between the MAC and SDR XGMII RX
interface.
Lane 0–[7:0]/[8]
Lane 1–[16:9]/[17]
Lane 2–[25:18]/[26]
Lane 3–[34:27]/[35]
lane 4–[43:36]/[44]
Lane 5–[52:45]/[53]
Lane 6–[61:54]/[62]
Lane 7–[70:63]/[71]
Table 3–8
XGMII Signal Name
XGMII Signal Name
for the mapping of the xgmii_rx_dc data and control to the
Description
Lane 5 control
Lane 6 data
Lane 6 control
Lane 7 data
Lane 7 control
Lane 0 data
Lane 0 control
Lane 1 data
Altera Transceiver PHY IP Core User Guide
Description
Description
3–7