IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 91

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Custom PHY IP Core
Interfaces
Table 7–12. Low Latency PHY IP Core Registers (Part 3 of 3)
Table 7–13. Clock Signals
December 2010 Altera Corporation
0x082
0x083
0x084
0x085
pll_ref_clk
rx_coreclkin
tx_coreclkin
pipe_pclk
Word
Addr
Clock Interface
[31:1]
[31:6]
[31:1]
[31:4]
[5:1]
Bits
[0]
[0]
[0]
[0]
[1]
[2]
[3]
Signal Name
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table 7–13
reference clock, pll_ref_clk, drives a PLL inside the PHY-layer block, and a PLL
output clock, rx_clkout (described in
command, and status inputs and outputs.
R
pcs8g_tx_status
tx_phase_comp_fifo_error
pcs8g_tx_control
tx_invpolarity
tx_bitslipboundary_select
Reserved.
rx_invpolarity
pcs8g_rx_wa_control
rx_enapatternalign
rx_bitreversal_enable
rx_bytereversal_enable
rx_bitslip
describes optional and required clocks for the Custom PHY. The input
Register Name
Direction
Output
Input
Input
Input
This is an optional clock to drive the coreclk of the RX PCS.
This is an optional clock to drive the coreclk of the TX PCS
Reference clock for the PHY PLLs. Frequency range is
50–700 MHz.
Clock for TX and RX parallel data, control, and status.
Reserved.
When set, indicates an TX phase compensation FIFO error.
From block: TX phase Compensation FIFO
Reserved.
When set, the TX interface inverts the polarity of the TX
data.
To block: 8B/10B encoder.
Sets the number of bits that the TX bit slipper needs to slip.
To block: Word aligner.
When set, the RX channels inverts the polarity of the
received data.
To block: 8B/10B decoder.
Reserved.
When set in manual word alignment mode, the word
alignment logic begins operation when this pattern is set.
To block: Word aligner.
When set, enables bit reversal on the RX interface.
To block: Word aligner.
When set, enables byte reversal on the RX interface.
To block: Byte deserializer.
Every time this register transitions from 0 to 1, the RX data
slips a single bit.
To block: Word aligner.
Table 7–10 on page
Description
Description
Altera Transceiver PHY IP Core User Guide
7–9) is used for all data,
—
7–13