IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 27

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: 10GBASE-R PHY IP Core
Interfaces
Table 3–10. 10GBASE-R Register Descriptions (Part 1 of 3)
December 2010 Altera Corporation
0x021
0x022
0x041
0x042
0x044
Word
Addr
[31:4,0]
[31:0]
[31:0]
[31:0]
[1:0]
Bit
[1]
[2]
[3]
R/W
RW
RW
RW
RW
RW
RW
W
R
R
Register Descriptions
Table 3–10
management interface using word addresses and a 32-bit embedded processor. A
single address space provides access to all registers.
cal_blk_powerdown
pma_tx_pll_is_locked
reset_ch_bitmask
reset_control (write)
reset_status (read)
reset_fine_control
reset_tx_digital
reset_rx_analog
reset_rx_digital
specifies the registers that you can access over the Avalon-MM PHY
Name
PMA Common Control and Status
Reset Control and Status
Writing a 1 to channel <n> powers down the calibration
block for channel <n>
Bit[P] indicates that the TX/CMU PLL (P) is locked to the
input reference clock.
Reset controller channel bitmask for digital resets. The
default value is all 1s. Channel <n> can be reset when
<n> = 1.
Writing a 1 to bit 0 initiates a TX digital reset using the reset
controller module. The reset affects channels enabled in the
reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX
digital reset of channels enabled in the
reset_ch_bitmask. Both bits 0 and 1 self-clear.
Reading bit 0 returns the status of the reset controller TX
ready bit. Reading bit 1 returns the status of the reset
controller RX ready bit.
You can use the reset_fine_control register to create
your own reset sequence. The reset control module,
illustrated in
reset sequence at power on and whenever the
phy_mgmt_clk_reset is asserted. Bits [31:4,0] are
reserved.
Writing a 1 causes the internal TX digital reset signal to be
asserted, resetting all channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
Writing a 1 causes the internal RX digital reset signal to be
asserted, resetting the RX analog logic of all channels
enabled in reset_ch_bitmask. You must write a 0 to
clear the reset condition.
Writing a 1 causes the RX digital reset signal to be
asserted, resetting the RX digital channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
Figure 1–1 on page
Description
Altera Transceiver PHY IP Core User Guide
1–2, performs a standard
3–9