IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 96

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

8–2
Device Family Support
Performance and Resource Utilization
Parameter Settings
Table 8–2. General Options
Altera Transceiver PHY IP Core User Guide
Device family
Number of lanes
Mode of operation
Phase compensation FIFO mode
Serialization factor
Data rate
Input clock frequency
Name
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■
■
Table 8–1
families.
Table 8–1. Device Family Support
Accurate resource utilization numbers are not available at this time.
To configure the Low Latency PHY IP core in the parameter editor, click Installed
Plug-Ins > Interfaces > Transceiver PHY > Low Latency PHY v10.1.
Table 8–2
Stratix V devices
Other device families
Final support—Verified with final timing models for this device.
Preliminary support—Verified with preliminary timing models for this device.
Device Family
shows the level of support offered by the PMA IP core for Altera device
lists the settings available on General Options tab.
Stratix V
1-32
Duplex
RX
TX
None
Embedded
8, 10, 16, 20, 32,
40, 50, 64, 66
600–12500 Mbps
60–700 MHz
Value
This IP core is only available Stratix V. Arria II GX, Arria II GZ,
HardCopy IV GX, and Stratix IV GX devices are not supported in
this release.
Number of channels, default value is 1. For Stratix V devices, the
valid range is 1–24 for the non-bonded mode and 1–5 for the
bonded mode.
Specifies the mode of operation as Duplex, RX, or TX mode.
When you select Embedded the PCS includes the phase
compensation FIFO and byte serializer, if required, to double the
data width. Default is None.
This option indicates the parallel data interface width. The
maximum width for Stratix IV devices is 40 bits. The 64- and
66-bit options are not available in the current release.
Specifies the data rate in Mbps. If you choose Bonded mode on
the Additional Options tab, the maximum data rate is 800 Mbps.
TX PLL input reference frequency in MHz. The allowed range
depends on the device you choose.
Preliminary
No support.
Description
Support
Chapter 8: Low Latency PHY IP Core
December 2010 Altera Corporation
Device Family Support