IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 12

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–6
Altera Transceiver PHY IP Core User Guide
1
The reset controller also includes a signal to power down the PLLs and transceiver
channels:
■
The Quartus
which takes effect when you configure the Stratix IV or Stratix V device. All unused
channels and blocks consume no power, reducing overall power consumption.
Table 1–2
Table 1–2. Bonding Requirements
The precise sequence of events that occurs to reset the transceiver PHY depends upon
the configuration chosen. The reset sequence for configurations that only include TX
channels is far simpler because it does not require the RX analog logic to recover the
clock from the input data stream or to perform offset cancellation.
illustrates the critical signals of the reset circuitry for a duplex PHY. As this figure
illustrates, the typical reset sequence includes the following steps:
1. After the PLL locks, tx_ready is asserted.
2. After offset cancellation completes rx_oc_busy is deasserted. (Offset cancellation
10GBASE-R
XAUI
Interlaken < ×4
Interlaken > ×4
PCI Express ×1
PCI Express ×2, ×4, ×8
Custom PHY
Low Latency PHY
Note to
(1) You can choose either bonded or non-bonded clocks for the Custom and Low Latency PHY IP cores to meet the
pll_powerdown—This signal powers down a single clock generation circuit.
pll_powerdown is only asserted during a full reset sequence, which is only possible
when the device enters user mode or when you assert and deassert the PHY
management interface reset input.
corrects for process variations which may result in analog voltages that are offset
from the required ranges.)
requirements of your design.
Table
lists the bonding requirements for the protocol-specific PHYs.
Protocol
1–2:
®
(1)
II software automatically selects the power-down channel feature,
(1)
Bonded
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December 2010 Altera Corporation
Non-Bonded
Figure 1–4
Chapter 1: Introduction
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Reset Controller