IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 111

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 10: Migrating from Stratix IV to Stratix V
PCI Express PHY (PIPE)
Table 10–3. Comparison of ALTGX Megafunction and PCI Express PHY (PIPE) Parameters (Part 2 of 2)
Table 10–4. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 1 of 3)
December 2010 Altera Corporation
Train receiver CDR from pll_inclk (false)
Tx PLL bandwidth mode (Auto)
Rx CDR bandwidth mode (Auto)
Acceptable PPM threshold (
Analog Power(VCCA_L/R) (Auto)
Reverse loopback option (No loopback)
Enable static equalizer control (false)
DC gain (1)
Rx Vcm (0.82)
Force signal detection (Off)
Signal Detect threshold (4)
Use external receiver termination (Off)
Rx term (100)
Transmitter buffer power(VCCH) (1.5)
Tx Vcm (0.65)
Use external transmitter termination (Off)
Tx Rterm (100)
VCO control setting (5)
Pre-emphasis 1st post tap (18)
Pre-tap (0)
2nd post tap (0)
DPRIO - Vod, Pre-em, Eq and EyeQ (Off)
DPRIO - Channel and Tx PLL Reconfig (Off)
pll_inclk
rx_cruclk
tx_coreclk
rx_coreclk
tx_clkout/coreclkout
(Note 1)
ALTGX Parameter Name (Default Value)
Stratix IV GX Device Signal Name
Port Differences
Table 10–4
Stratix V GX/GS devices. PIPE standard ports remain, but are now prefixed with
pipe_. Clocking options are simplified to match the PIPE 2.0 specification.
±
300)
lists the differences between the top-level signals in Stratix IV GX and
Reference Clocks and Resets
PCI Express PHY (PIPE) Parameter Name
pll_ref_clk
pipe_pclk
Not available in MegaWizard Interface
Stratix V Device Signal Name
Not available
Not available
Not available
Altera Transceiver PHY IP Core User Guide
Use assignment editor to
make these assignments
1
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
1
Comments
Width
10–5