IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 35

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Release Information
December 2010 Altera Corporation
f
The Altera XAUI PHY IP core implements the
extend the operational distance of the XGMII interface and reduce the number of
interface signals. XAUI extends the physical separation possible between the 10 Gbps
Ethernet MAC function implemented in an Altera FPGA and the Ethernet standard
PHY component on a PCB to one meter.
Figure 4–1
Stratix V devices.
Figure 4–1. XAUI PHY with Hard IP PCS and PMA in Stratix IV GX or Stratix V Devices
For Stratix IV GX and GT devices, you can choose a hard XAUI physical coding
sublayer (PCS) and physical media attachment (PMA), or a soft XAUI PCS and PMA
in low latency mode. You can also combine both hard and soft PCS configurations in
the same device, using all six channels in a transceiver bank. In Quartus II version
10.1, the PCS is only available in soft logic for Stratix V devices.
For more detailed information about the XAUI transceiver channel datapath,
clocking, and channel placement, refer to the “XAUI” section in the
Protocol Configurations in Stratix V Devices
Table 4–1
Table 4–1. XAUI Release Information (Part 1 of 2)
Version
Release Date
Ordering Codes
Product ID
Arria II GX, Cyclone IV GX, Stratix IV GX or GT, or Stratix V FPGA
72 bits @ 156.25 Mbps
Control & Status
SDR XGMII
provides information about this release of the XAUI PHY IP core.
Avalon-MM
illustrates the top-level blocks of the XAUI PHY for Stratix IV GX or
Item
(Note 1)
XAUI IP Core
Phase Comp
Word Aligner
8B/10B
PCS
chapter of the Stratix V Device Handbook.
IPR-XAUIPCS (renewal)–soft PCS
IP-XAUIPCI (primary)–soft PCS
IEEE 802.3 Clause 48
Hard PMA
December 2010
4. XAUI PHY IP Core
Description
Altera Transceiver PHY IP Core User Guide
00D7
10.1
4 x 3.125 Gbps serial
specification to
Transceiver
4
4