IPR-ED8B10B Altera, IPR-ED8B10B Datasheet

no-image

IPR-ED8B10B

Manufacturer Part Number
IPR-ED8B10B
Description
IP CORE Renewal Of IP-ED8B10B
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-ED8B10B

Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
101 Innovation Drive
San Jose, CA 95134
www.altera.com
8B10B Encoder/Decoder MegaCore
Function User Guide
Software Version:
Document Date:
November 2009
9.1

Related parts for IPR-ED8B10B

IPR-ED8B10B Summary of contents

Page 1

... Innovation Drive San Jose, CA 95134 www.altera.com 8B10B Encoder/Decoder MegaCore Function User Guide Software Version: 9.1 Document Date: November 2009 ...

Page 2

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warran- ty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

Page 3

... Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Chapter 3. Specifications Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–ii © November 2009 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide Preliminary Contents ...

Page 4

... Encoder/Decoder MegaCore Function User Guide © November 2009 Altera Corporation Preliminary Contents ...

Page 5

... Altera does not verify compilation with MegaCore function versions older than one release." Device Family Support MegaCore functions provide either full or preliminary support for target Altera device families: ■ Full support means the MegaCore function meets all functional and timing requirements for the device family and may be used in production designs. ■ ...

Page 6

... Support for OpenCore Plus evaluation. ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators. General Description Encoders and decoders are used for physical layer coding for Gigabit Ethernet, Fibre Channel, and other applications. The 8b/10b encoder takes byte inputs, and generates a direct current (DC) balanced stream (equal number of 1s and 0s) with a maximum run length of 5 ...

Page 7

... Performance and Resource Utilization Performance and Resource Utilization This section lists the resource utilization and performance of the 8B10B Encoder/Decoder MegaCore function in different Altera device families. These results were obtained using the Quartus replacement feature disabled. Enabling this feature produces a smaller but slower MegaCore function. Table 1– ...

Page 8

... After you purchase a license for 8B10B Encoder/Decoder, you can request a license file from the Altera website at computer. When you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative. f For more information on OpenCore Plus hardware evaluation using the 8B10B ...

Page 9

... The valid output is forced low (deasserted). ■ For the decoder: ■ The ena input signal is forced low (deasserted). ■ The dataout output is forced to all zeros. ■ The valid output is forced low (deasserted). ■ © November 2009 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide Preliminary 1–5 ...

Page 10

... Encoder/Decoder MegaCore Function User Guide Chapter 1: About This MegaCore Function © November 2009 Altera Corporation Preliminary Installation and Licensing ...

Page 11

... Function, follow these additional steps: 1. Set up licensing. 2. Generate a programming file for the Altera 3. Program the Altera device(s) with the completed design. 8B10B Encoder /Decoder Walkthrough This walkthrough shows you how to create an 8B10B Encoder/Decoder MegaCore function using the MegaWizard interface and the Quartus II software. After generating a custom variation of the 8B10B Encoder/Decoder MegaCore function, you can incorporate it into your overall project ...

Page 12

... To create a new project follow these steps: 1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. Alternatively, you can use the Quartus II Web Edition software. ...

Page 13

... Register inputs/outputs check box for a single-cycle latency. 1 The Decoder always has registered inputs and outputs. 3. Click Next (or the EDA tab) to display the simulation setup page . © November 2009 Altera Corporation Plug-In Manager by choosing the MegaWizard Plug-In ® 8B10B Encoder/Decoder MegaCore Function User Guide Preliminary ...

Page 14

... MegaCore function and for each SOPC Builder system. However, some more complex SOPC Builder components generate a separate .qip file, so the system .qip file references the component .qip file. 8B10B Encoder/Decoder MegaCore Function User Guide 8B10B Encoder /Decoder Walkthrough © November 2009 Altera Corporation Preliminary Chapter 2: Getting Started ...

Page 15

... Select TCL Scripts (Tools menu). 2. Select the applicable Tcl file for your variation: <variation name>_constraints. tcl 3. Click Run. or © November 2009 Altera Corporation (Note 1) Filename (2) Quartus II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor ...

Page 16

... For more information on IP functional simulation models, refer to the Altera IP in Third-Party Simulation Tools Altera also provides a Verilog HDL demonstration testbench, including scripts to compile and run the demonstration testbench using a variety of simulators and models. This testbench demonstrates the typical behavior of an 8B10B MegaCore function, and how to instantiate a model in a design ...

Page 17

... You can use the Quartus II software to compile your design. Refer to Quartus II Help for instructions on compiling your design. Program a Device After you have compiled your design, program your targeted Altera device, and verify your design in hardware. © November 2009 Altera Corporation 8B10B Encoder/Decoder MegaCore Function User Guide Preliminary 2– ...

Page 18

... Encoder/Decoder MegaCore Function User Guide © November 2009 Altera Corporation Preliminary Chapter 2: Getting Started Program a Device ...

Page 19

... To guarantee neutral average disparity, a positive running disparity must be followed by neutral or negative disparity; a negative running disparity must be followed by neutral or positive disparity. © November 2009 Altera Corporation function consists of an encoder (ENC8B10B) and a decoder ® Figure 3–2 on page 3– ...

Page 20

... Encoder/Decoder MegaCore Function User Guide Figure 3–2 on page 3–2 Egress Transport Network GFP Data Stream GFP GFP Mapper Demapper (64B/65B Encoded) Preliminary Chapter 3: Specifications Functional Description for an example. Gigabit Ethernet Stream 8B/10B Encoder (8B/10B Encoded) © November 2009 Altera Corporation ...

Page 21

... Although the 10B_ERR code is considered invalid special character, it does not cause the kerr signal to be asserted. Idle (K28.5) characters can be automatically inserted when ena is not asserted by asserting the idle_ins input. © November 2009 Altera Corporation Table 3–1 on page 3–3). The x value corresponds to the five-bit group, K28.0 K28 ...

Page 22

... If the encoded words are to be transmitted serially, the result of encoding datain[15:8] should be transmitted first. 8B10B Encoder/Decoder MegaCore Function User Guide clk kerr reset_n dataout [9:0] kin ena valid idle_ins rdout datain [7:0] rdin rdcascade rdforce © November 2009 Altera Corporation Preliminary Chapter 3: Specifications Functional Description Figure 3–4 on ...

Page 23

... The encoded value—corresponding to the values of datain and kin sampled by the encoder on rising edge n—is output shortly after rising edge n, and is available to be sampled on the rising edge of clock cycle n+1. (See Figure 3–6). © November 2009 Altera Corporation clk kerr reset_n kin [1] dataout [19:10] ...

Page 24

... K codes, and Preliminary Chapter 3: Specifications Functional Description Figure 3–1 on page 3–1 for an © November 2009 Altera Corporation ...

Page 25

... The decoded value—corresponding to the value of datain sampled by the decoder on rising edge n—is output shortly after rising edge n+1, and is available to be sampled on the rising edge of clock cycle n+2. (See Figure 3–8. Decoder Timing Diagram © November 2009 Altera Corporation clk reset_n idle_del ...

Page 26

... Cascaded running disparity. Used when encoders are cascaded. rdcascade 8B10B Encoder/Decoder MegaCore Function User Guide “Parameterize” on page Parameter Encoder or Decoder On for a three cycle latency. Off for a one-cycle latency. Description Preliminary Chapter 3: Specifications Parameters 2–3). Value © November 2009 Altera Corporation ...

Page 27

... Output Running disparity output. The current running disparity (after decoding the word rdout present on the dataout output). Output Cascaded running disparity. Used when decoders are cascaded. rdcascade © November 2009 Altera Corporation Description 8B10B Encoder/Decoder MegaCore Function User Guide Preliminary 3–9 ...

Page 28

... Encoder/Decoder MegaCore Function User Guide © November 2009 Altera Corporation Preliminary Chapter 3: Specifications Signals ...

Page 29

... For the most up-to-date information about Altera Contact Technical support Technical training Altera literature services Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. © November 2009 Altera Corporation Additional Information Changes Made and Figure 3–6. ® ...

Page 30

... A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press Enter. The feet direct you to more information about a particular topic. Preliminary Typographic Conventions © November 2009 Altera Corporation ...

Related keywords