IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 28

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–10
Table 3–10. 10GBASE-R Register Descriptions (Part 2 of 3)
Altera Transceiver PHY IP Core User Guide
0x061
0x063
0x064
0x065
0x066
0x067
0x080 [31:0]
0x081
0x082
Word
Addr
[2]
[3]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
Bit
RW
RW
RW
R
R
R
R
R
R
R
R/W
RW
RW
RW
R
R
R
pma_serial_loopback
pma_rx_signaldetect
pma_rx_set_locktodata
pma_rx_set_locktoref
pma_rx_is_lockedtodata
pma_rx_is_lockedtoref
INDIRECT_ADDR
RCLR_ERRBLK_CNT
RCLR_BER_COUNT
PCS_STATUS
HI_BER
BLOCK_LOCK
TX_FIFO_FULL
RX_FIFO_FULL
RX_SYNC_HEAD_ERROR
RX_SCRAMBLER_ERROR
Name
10GBASE-R PCS–Stratix IV Devices
PMA Channel Control and Status
Writing a 1 to channel <n> puts channel <n> in serial
loopback mode.
When asserted, the signal level circuit senses if the
specified voltage level exists at the receiver input buffer. Bit
<n> corresponds to channel <n>.
When set, programs the RX CDR PLL to lock to the
incoming data. Bit <n> corresponds to channel <n>.
When set, programs the RX CDR PLL to lock to the
reference clock. Bit <n> corresponds to channel <n>.
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode. Bit <n> corresponds to channel <n>.
When asserted, indicates that the RX CDR PLL is locked to
the reference clock. Bit <n> corresponds to channel <n>.
Provides for indirect addressing of all PCS control and
status registers. Use this register to specify the logical
channel address of the PCS channel you want to access.
When set to 1, clears the error block count register.
To block: Block synchronizer
When set to 1, clears the bit error rate (BER) register.
To block: BER monitor
When asserted indicates that the PCS link is up.
When asserted by the BER monitor block, indicates that the
PCS is recording a high BER.
From block: BER monitor
When asserted by the block synchronizer, indicates that the
PCS is locked to received blocks.
From Block: Block synchronizer
When asserted, indicates the TX FIFO is full.
From block: TX FIFO
When asserted, indicates the RX FIFO is full.
From block: RX FIFO
When asserted, indicates an RX synchronization error. This
signal is Stratix V devices only.
When asserted, indicates an RX scrambler error. This signal
is Stratix V devices only.
Description
Chapter 3: 10GBASE-R PHY IP Core
December 2010 Altera Corporation
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