IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 47

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: XAUI PHY IP Core
Interfaces
Table 4–12. Clock and Reset Signals
December 2010 Altera Corporation
pll_ref_clk
rx_analogreset
rx_digitalreset
tx_digitalreset
Clocks, Reset, and Powerdown
Signal Name
Figure 4–6
PCS and PMA blocks.
Figure 4–6. Clock Inputs and Outputs, Hard PCS
Figure 4–7
and PMA blocks.
Figure 4–7. Clock Inputs and Outputs, Soft PCS
Table 4–12
phy_mgmt_clk
pll_ref_clk
xgmii_tx_clk
xgmii_rx_clk
phy_mgmt_clk
pll_ref_clk
xgmii_tx_clk
xgmii_rx_clk
illustrates the clock inputs and outputs for the XAUI IP cores with soft PCS
illustrates the clock inputs and outputs for the XAUI IP cores with hard
describes the optional reset signals.
Direction
Input
Input
Input
Input
XAUI Soft IP Core
pma_pll_inclk
sysclk
XAUI Hard IP Core
Soft PCS
tx_coreclk
coreclkout
This is a 156.25 MHz reference clock that is used by the TX PLL and
CDR logic.
This signal resets the analog CDR and deserializer logic in the RX
channel. It is only available in the hard IP implementation.
PCS RX digital reset signal.
PCS TX digital reset signal.
Hard PCS
pma_tx_clkout
pma_rx_clkout
tx_clkout
rx_recovered_clk
pll_inclk
pll_ref_clk
PMA
Description
PMA
Altera Transceiver PHY IP Core User Guide
rx_cruclk
4
4
4 x 3.125 Gbps serial
4 x 3.125 Gbps serial
4
4
4–13