IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 73

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: PCI Express PHY (PIPE) IP Core
Interfaces
Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 4 of 4)
Table 6–8. PIPE Interface (Part 1 of 2)
December 2010 Altera Corporation
0x086
pll_ref_clk
fixedclk
pipe_txdetectrx_loopback
pipe_txelecidle
pipe_txdeemph
Word
Addr
PIPE Interface
Signal Name
[31:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
Bits
Table 6–8
R/W
R
R
R
R
R
R
Reserved
rx_rlv
rx_patterndetect
rx_disperr
rx_syncstatus
rx_errdetect
describes the signals in the PIPE interface.
Direction
Register Name
Sink
Sink
Sink
Sink
Sink
This is the 100 MHz input reference clock source for the PHY PLL. You can
optionally provide a 125 MHz input reference clock by setting the PLL
reference clock frequency parameter to 125 MHz.
A 125 MHz clock used for the receiver detect circuitry.
This signal instructs the PHY to start a receive detection operation. After
power-up asserting this signal starts a loopback operation. Refer to section
6.4 of the
a timing diagram.
This signal forces the transmit output to electrical idle. Refer to section 7.3
of the
timing diagrams.
Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it
selects the transmitter de-emphasis:
■
■
1'b0: -6 dB
1'b1: -3.5 dB
Intel PHY Interface for PCI Express (PIPE) Architecture
Intel PHY Interface for PCI Express (PIPE) Architecture
When set, indicates a run length violation.
From block: Word aligner.
When set, indicates that RX word aligner has achieved
synchronization.
From block: Word aligner.
When set, indicates that the received 10-bit code or data
group has a disparity error. When set, the corresponding
errdetect bits are also set.
From block: 8B/10B decoder.
When set, indicates that the RX interface is synchronized to
the incoming data.
From block: Word aligner.
When set, indicates that a received 10-bit code group has
an 8B/10B code violation or disparity error. It is used along
with Rx disparity to differentiate between a code violation
error and a disparity error, or both.
In PIPE mode, the PIPE specific output port called
pipe_rxstatus encodes the errors.
From block: 8B/10B decoder.
Description
Description
Altera Transceiver PHY IP Core User Guide
—
for
for
6–9