IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 83

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Custom PHY IP Core
Parameter Settings
Table 7–4. Word Aligner Options
December 2010 Altera Corporation
Word alignment mode
Enable run length violation
checking
Run length
Word Alignment
Name
The word aligner restores word boundaries of received data based on a predefined
alignment pattern. This pattern can be 7, 8, 10, 16, 20, or 32 bits long. The word
alignment module searches for a programmed pattern to identify the correct
boundary for the incoming stream.
Aligner tab.
Manual
Bit slipping
Automatic
synchronization
state machine
On/Off
40–640
Value
You can select 1 of the following 3 modes:
■
■
■
If you turn this option on, you can specify the run length which is the
maximum legal number of contiguous 0s or 1s.
Specifies the threshold for a run-length violation.
Manual—In this mode you enable the word alignment function by
asserting rx_enapatternalign using the Avalon-MM interface.
Word aligner starts searching for the alignment pattern as soon as
this control signal is asserted.
Bit Slip Mode—You can use bit slip mode to shift the word
boundary using the Avalon-MM interface. For every rising edge of
the rx_bitslip signal, the word boundary is shifted by 1 bit.
Each bit slip removes the earliest received bit from the received
data.
Automatic Synchronization State Machine Mode—In this mode,
word alignment is controlled by a programmable state machine.
This mode can only be used with 8B/10B encoding. The data width
at the word aligner can be 10 or 20 bits. You can specify the
following parameters:
■
■
■
■
■
10-bit pattern for use in the word alignment state machine.
Number of consecutive valid words before sync state is
reached: Specifies the number of consecutive valid words
needed to reduce the built up error count by 1. Valid values are
0–255.
Number of bad data words before loss of sync state: Specifies
the number of bad data words required for alignment state
machine to enter loss of sync state. Valid values are 0–255.
Number of valid patterns before sync state is reached:
Specifies the number of consecutive patterns required to
achieve synchronization.Valid values are 0–255.
Word alignment pattern length: Allows you to specify a 7- or
Word alignment pattern: Allows you to specify a word
alignment pattern.
Table 7–4
lists the settings available on the Word
Description
Altera Transceiver PHY IP Core User Guide
7–5