IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 97

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 8: Low Latency PHY IP Core
Parameter Settings
Table 8–2. General Options
Table 8–3. Additional Options (Part 1 of 2)
December 2010 Altera Corporation
Enable lane bonding
Avalon data interfaces
Enable tx_coreclkin
Enable rx_coreclkin
Enable TX bitslip
Select 10G PCS
Deserializer block width
Deserializer actual width
Name
Name
(Note 1)
The parameters on the Additional Options tab control clocking and PCS options.
Both bonded (×N) and non-bonded modes are available. In bonded modes, a single
PLL can drive all channels as
Table 8–3
describes the options available on the Additional Options tab.
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Auto
Single
Double
Auto
Single
Double
Value
Value
When you turn this option on, tx_coreclk connects to the write
clock of the TX phase compensation FIFO and you can clock the
parallel TX data generated in the FPGA fabric using this port. This
port allows you to clock the write side of the TX phase
compensation FIFO with a user-provided clock, either the FPGA
fabric clock, the FPGA fabric-TX interface clock, or the input
reference clock. This option must be turned on if the serialization
factor is not 40 in Stratix V devices when10G PCS is used.
When you turn this option on, rx_coreclk connects to the read
clock of the RX phase compensation FIFO and you can clock the
parallel RX output data using rx_coreclk. This port allows you to
clock the read side of the RX phase compensation FIFO with a
user-provided clock, either the FPGA fabric clock, the FPGA fabric
RX interface clock, or the input reference clock.
When set, the word aligner operates in bit-slip mode. This option is
available for Stratix V devices using the 10G PCS.
This option selects the higher throughput 10G PCS rather than the
standard PCS. This option is available for Stratix V devices.
Specifies the datapath width between the transceiver PCS and
PMA. The deserializer clocks in serial input data from the RX buffer
using the high-speed recovered clock and deserializes it using the
low-speed parallel recovered clock. The Auto mode is available in
the current release so that the Quartus II software determines the
correct setting.
Indicates the selected deserializer width.
When enabled, the PMA uses bonded clocks.
When you turn this option on, there is a separate Avalon-ST bus
for each lane which includes the control and status signals for that
lane. Layout and transmission of data is big endian. When you
turn this option off, the TX and RX interfaces are configured as a
single data and control bus, regardless of the number of lanes.
The layout and transmission of the TX and RX buses is little
endian.
Figure 1–2 on page 1–4
Description
Description
illustrates.
Altera Transceiver PHY IP Core User Guide
8–3