IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 95

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
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The Altera Low Latency IP core receives and transmits differential serial data,
recovering the RX clock from the RX input stream. The PMA connects to a simplified
PCS that whose single function doubles the width of the TX and RX datapaths. An
Avalon-ST interface is used for TX and RX data for the MAC interface. An
Avalon-MM interface provides access to control and status information.
Figure 8–1
Figure 8–1. Low-Latency PHY IP Core—Stratix IV and Stratix V Devices
Because the Low latency PHY IP core bypasses much of the standard PCS, it
minimizes the PCS latency.
low latency PCS.
Table 8–1. TX Datapath Latency
For more detailed information about the Low Latency datapath and clocking, refer to
the “Standard PCS Custom and Low Latency Configurations” section in the
Transceiver Configuration Datapath in Stratix V Devices
Handbook.
For more information about the Avalon-MM and Avalon-ST protocols, including
timing diagrams, refer to the
TX Phase Compensation FIFO
Byte Serializer
Word Aligner
Byte Serializer
Byte Ordering
RX Phase Compensation FIFO
Notes to
(1) These numbers are preliminary, pending device characterization.
(2) This value depends on whether the block is enabled or disabled.
(3) This value depends on the configuration mode.
Stratix IV or Stratix V FPGA
Embedded
Table
Controller
MAC
to
to
illustrates the top-level modules of the Low Latency PHY IP core.
Block
8–1:
Control & Status
Avalon-MM
Avalon-ST
Table 8–1
(Note 1)
Avalon Interface
Normal Latency
Byte Serializer
Phase Comp
the compares the latency of the standard and
TX Channel
RX Channel
3–7
PCS
4–5
1–2
1–2
1–3
3–4
8. Low Latency PHY IP Core
(3)
Specifications.
chapter of the Stratix V Device
Altera Transceiver PHY IP Core User Guide
PMA
Low Latency
0–2
Tx serial data
Rx serial data
3–5
2–3
1
1
0
Custom
(2)