IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 24

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–6
Table 3–5. SDR XGMII TX Inputs
Table 3–6. Mapping from XGMII TX Bus to XGMII SDR Bus (Part 1 of 2)
Altera Transceiver PHY IP Core User Guide
xgmii_tx_dc<n>[71:0]
tx_ready
xgmii_tx_clk
Note to
(1) <n> is the channel number
xgmii_tx_dc[7:0]
xgmii_tx_dc[8]
xgmii_tx_dc[16:9]
xgmii_tx_dc[17]
xgmii_tx_dc[25:18]
xgmii_tx_dc[26]
xgmii_tx_dc[34:27]
xgmii_tx_dc[35]
xgmii_tx_dc[43:36]
xgmii_tx_dc[44]
xgmii_tx_dc[52:45]
Signal Name
Table
SDR XGMII TX Interface
3–5:
Signal Name
f
Table 3–5
driven from the MAC to the PCS. This is an Avalon-ST sink interface.
For more information about the Avalon-ST protocol, including timing diagrams, refer
to the
Table 3–6
interface.
Direction
Avalon Interface
Output
Input
Sink
describes the signals in the SDR XGMII TX interface. These signals are
provides the mapping from the XGMII TX interface to the XGMII SDR
(Note 1)
xgmii_sdr_data[7:0]
xgmii_sdr_ctrl[0]
xgmii_sdr_data[15:8]
xgmii_sdr_ctrl[1]
xgmii_sdr_data[23:16]
xgmii_sdr_ctrl[2]
xgmii_sdr_data[31:24]
xgmii_sdr_ctrl[3]
xgmii_sdr_data[39:32]
xgmii_sdr_ctrl[4]
xgmii_sdr_data[47:40]
Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of
data and 1 bit of control.
■
■
■
■
■
■
■
■
Refer to
xgmii_sdr_data and xgmii_sdr_ctrl signals.
Asserted when the TX channel is ready to transmit data. Because the
readyLatency on this Avalon-ST interface is 0, the MAC may drive
xgmii_tx_dc_valid as soon as tx_ready is asserted.
The XGMII TX clock which runs at 156.25 MHz.
Lane 0–[7:0]/[8]
Lane 1–[16:9]/[17]
Lane 2–[25:18]/[26]
Lane 3–[34:27]/[35]
lane 4–[43:36]/[44]
Lane 5–[52:45]/[53]
Lane 6–[61:54]/[62]
Lane 7–[70:63]/[71]
Specifications.
Table 3–6
XGMII Signal Name
for the mapping of the xgmii_tx_dc data and control to the
Description
Lane 0 data
Lane 0 control
Lane 1 data
Lane 1 control
Lane 2 data
Lane 2 control
Lane 3 data
Lane 3 control
Lane 4 data
Lane 4 control
Lane 5 data
Chapter 3: 10GBASE-R PHY IP Core
December 2010 Altera Corporation
Description
Interfaces