IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 104

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

9–2
Register Descriptions
Table 9–1. Dynamic Reconfiguration Control and Status Registers (Part 1 of 2)
Altera Transceiver PHY IP Core User Guide
0x108
0x109
0x10A
0x10B
Offset
[31:10]
[9:0]
[31:10]
[9:0]
[31:10]
[9]
[8]
[7:2]
[1]
[0]
[31:5]
[4:0]
Bits
f
1
R/W
RW
RW
RW
RW
RW
RW
During power-up, the Stratix IV GX devices perform offset cancellation for the RX
channels to correct for process variations. You cannot reconfigure the PMA analog
settings before this process completes.
Refer to
duplex channel.
Table 9–1
registers.
—
—
—
—
—
R
Reserved
logical_channel_address
Reserved
physical_channel_address
Reserved
status
Reserved
tx_rx_word_offset
Figure 1–4 on page 1–7
describes the analog Transceiver Reconfiguration control and status
Register Name
which illustrates the critical signals for the reset of a
The logical channel address. Must be specified when
performing dynamic updates.
The physical channel address.
Error. When asserted, indicates an error. This bit is
asserted if any of the following conditions occur:
■
■
Busy. When asserted, indicates that the a reconfiguration
operation is in progress.
Reserved.
Read. Writing a 1 to this bit specifies a read operation.
Write. Writing a 1 to this bit specifies a write operation.
Specifies the offset of the PMA analog setting to be
reconfigured. The following analog settings are available:
■
■
■
■
■
■
■
■
0–V
1–Pre-emphasis pre-tap
2–Pre-emphasis first post-tap
3-Pre-emphasis second post-tap
4-15–reserved
16–RX equalization DC gain
17–RX equalization control
13-18–reserved
The channel address is invalid.
The pre-emphasis value is invalid.
OD
Chapter 9: Transceiver Reconfiguration Controller
Description
December 2010 Altera Corporation
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—
—
—
Register Descriptions