tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 90

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
(3) Branch to the Exception Handler
(4) Interrupt Acceptance Signal
An interrupt vector address differs depending on combination of the Status<BEV> bit and the
Cause<IV> bit.
Status<BEV> is set to “1” after reset. Keep the setting if you set an exception vector address in the
internal ROM.
The Cause<IV> bit is undefined after reset. Setting this bit to “1” is required. By setting this bit to “1”
the vector addresses of interrupt exceptions and other exceptions can be distinguished.
When the CPU detects the interrupt, it sends a signal, which indicates the interrupt is accepted, to INTC.
By the signal, INTC holds the interrupt level and interrupt number that have the highest priority at that
time. See “6.5.2.3 Detection by CG” for INTC operation.
IV = 0
IV = 1
TMP19A44(rev1.3) 6-40
0x8000_0180
0x8000_0200
BEV = 0
0xBFC0_0380
0xBFC0_0400
BEV = 1
TMP19A44
2010-04-01