tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 63

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.2.2
6.2.2.1
CPU/ CG handles reset
Reset Exception/ NMI Handling
Reset exception/ NMI
CPU branches off to
factor is generated
The following shows how a reset exception and NMI are handled.
CPU detects reset
exception handler
exception/ NMI.
exception/ NMI
Processing
Flowchart
indicates hardware handling.
TMP19A44(rev1.3) 6-13
A reset exception/ NMI factor is generated.
The CPU detects reset exception/ NMI.
The CPU/ CG handles the reset exception/ NMI.
○Reset exception
○NMI
The CPU branches off to the reset exception vector address
(0xBFC0_0000).
All the special function registers of the peripherals are
initialized.
The following bits in the CP0 register are automatically set.
The following bits in the CP0 register and CG are
automatically set.
CP0:
CP0:
CP0:
CP0:
CP0:
CP0:
CP0:
CP0:
CP0:
CP0:
CP0:
CG:
Status<ERL>
ErrorEPC
Status<BEV>
Status<NMI>
Status<RP>
SSCR<PSS>
Status<ERL>
ErrorEPC
Status<NMI>
Cause<BD>
NMIFLG
SSCR<PSS>
indicates software handling.
Details
←
←
←
←
←
←
←
←
←
←
←
←
“1”
“PC of exception”(Note)
“1”
“0”
“0”
Register
“1”
“PC of exception” (Note)
“1”
“1/0” (Note)
“1
corresponding bit”
Register
(when exception occurs)
(when
occurs)
TMP19A44
is
set
set
2010-04-01
set
exception
number
number
to