tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 402

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (HSIO)
(Note)
Data write timing to send
buffer or shift register
•
If the CTS signal is set to "H" during transmission, the next data transmission is
suspended after the current transmission is completed.
Data transmission starts on the first falling edge of the TXDCLK clock after CTS is set
to "L."
Handshake function
TXDCLK
SIOCLK
CTS
TXD
The H CTS pin enables frame by frame data transmission so that overrun errors can be
prevented. This function can be enabled or disabled by HSC0MOD0 <CTSE>.
When the H CTS0 pin is set to the "H" level, the current data transmission can be completed
but the next data transmission is suspended until the H CTS0 pin returns to the "L" level.
However in this case, the HINTTX0 interrupt is generated, the next transmit data is requested
to the CPU, data is written to the send buffer, and it waits until it is ready to transmit data.
Although no H RTS pin is provided, a handshake control function can be easily implemented
by assigning a port for the H RTS function. By setting the port to "H" level upon completion
of data reception (in the receive interrupt routine), the transmit side can be requested to
suspend data transmission.
Transmission is
suspended during
this period
Fig. 15-7 CTS (Clear to Send) Signal Timing
Transmit side
13
Fig. 15-6 Handshake Function
TMP19A44(rev1.3) 15-12
H CTS
HTXD
14
15
16
1
start bit
2
3
HRXD
H RTS (Any port)
Receive side
14
15
TMP19A44
16
1
bit 0
2010-04-01
2
3