tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 82

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
(1) Disabling interrupt by CPU
(2) CPU registers setting
(3) Preconfiguration 1 (Interrupt from external pin)
bit is set to be interrupt-disabled after reset.
high-speed processing.
be distinguished.
allows the pin to be used as the function pin. Clearing PnCR [m] to “0” allows the pin to be used as the input
port.
To make the CPU for not accepting any interrupt, write “0” to the Status<IE> bit of the CP0 register. This
The following shows how to make IE bit “0”.
You can select one of them. We recommend No. 2 and No. 4 that prevent code increase and enable
Configure the CP0 register.
By setting the Cause<IV> bit to “1” the vector addresses of interrupt exceptions and other exceptions can
Write “1” to the Status<IM4:2> bits to enable an interrupt from INTC.
Clear the SSCR<SSD> bit to “0” when using a shadow register.
Set the port of the corresponding pin. Setting PnFCx [m] of the corresponding port function register to “1”
1.
2.
3.
4.
(Note)
● CPU register
Status<IE>
Set “0” to the Status<IE> bit of the CP0 register by 32 bit ISA MTC0 instruction.
Set “0” to the IER bit of the CP0 register by 32 bit ISA MTC0 instruction.
Set “0” to the Status<IE> bit of the CP0 register by 16 bit ISA MTC0 instruction.
Execute 16 bit ISA DI instruction.
●CPU register
Cause<IV>
Status<IM>
SSCR<SSD>
● Port register
PnFCx<PnmFx>
PnCR<PnmC>
n: port number
m: corresponding bit
x: function register number
TMP19A44(rev1.3) 6-32
←
←
←
←
←
←
“0” (interrupt disabled)
“1”
“111”
“0”
“1”
“0”
TMP19A44
2010-04-01