tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 242

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

External Bus Interface
(3) Time that it takes before ALE is asserted
When the external bus of the TMP19A44 is used as a multiplexed bus, the ALE width (assert time) can be
specified by using the system control register
mode, ALE is not output, but the time from when an address is established to the assertion of the RD or
During a reset, <ALESEL 1:0> = "1" is set and the RD or
(internal) clocks after an address is established. If <ALESEL 1:0> is cleared to "0," the RD or
is asserted at a point of one system (internal) clock after an address is established. This assert setting
cannot be established for each block in an external area and the same setting is commonly used in an
external address space.
WR
signal is different depending on the
A[23:0]
D[15:0]
RD
Fig. 8.8 ALE Assert Ttiming in Separate Bus Mode
<ALESEL>="0"
TMP19A44 (rev1.3) 8-14
address
tsys
data
BUSCR<ALESEL1:0>
BUSCR<ALESEL1:0>
<ALESEL>="1"
address
WR
.
signal is asserted as a point of two system
in the CG. In the case of a separate bus
data
TMP19A44
2010-04-01
WR
signal