tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 666

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tmp19a44fda

Manufacturer Part Number
tmp19a44fda
Description
32bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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Electrical Characteristics
OUTPUT DATA
INPUT DATA
SCK period
SCK Clock High width(input)
SCKClock Low width(input)
SO data to SCK rise
SO data hold after SCK rise
SI data valid to SCK rise
SI data hold after SCK rise
SCK period (programmable)
SO data to SCK rise
SO data hold after SCK rise
SI data valid to SCK rise
SI data hold after SCK rise
(2) Clock-Synchronous 8-Bit SIO mode
SCLK
TxD
TxD
denotes the value of n programmed into the SCK (SCL output frequency select) field in the
SBI0CR1.
3) SCK Input mode
4) SCK Output mode
In the tables below, the letters x represent the fsys cycle periods, respectively. The letter n
The electrical specifications below are for an SCK signal with a 50% duty cycle.
Parameter
Parameter
t
t
OSS
SRD
VALID
0
t
0
SCY
TMP19A44 (rev1.3) 27-26
tSCY
TscH
TscH
tOSS
tOHS
tSRD
tHSR
Symb
Symb
t
t
t
t
t
SCY
OSS
OHS
SRD
HSR
ol
ol
VALID
16x
tSCY /2
tSCY /2
(tSCY/2) − (6x + 20)
(tSCY/2) + 4x
0
4x + 10
1
1
(t
(t
SCY
SCY
2x + 30
t
2
HSR
Min
n
Min
t
Equation
/2) − 20
/2) − 20
・T
0
SCH
Equation
t
OHS
t
SCL
Max
VALID
Max
2
2
40/ 80 MHz
Min
400
200
200
30
300
0
110
800
380
380
40/ 80 MHz
55
Min
0
TMP19A44
Max
Max
ns
ns
ns
ns
ns
ns
ns
VALID
3
Unit
Unit
3
ns
ns
ns
ns
ns
2010-04-01

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