tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 606

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Flash Memory Operation
2.
1st byte. The boot program echoes back the first byte: 86H for UART mode and 30H for I/O Interface
mode.
3.
RAM Transfer command is 10H.
4.
3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error.
If there was a receive error, the boot program transmits x8H and returns to the state in which it waits for
a command again. In this case, the upper four bits of the acknowledge response are undefined — they
hold the same values as the upper four bits of the previously issued command. When the SIO0 is
configured for I/O Interface mode, the boot program does not check for a receive error.
If the 3rd byte is equal to any of the command codes listed in Table 24.4, the boot program echoes it
back to the controller. When the RAM Transfer command was received, the boot program echoes back
a value of 10H and then branches to the RAM Transfer routine. Once this branch is taken, a password
check is done. Password checking is detailed in Section “Password”.
If the 3rd byte is not a valid command, the boot program sends back x1H to the controller and returns to
the state in which it waits for a command again. In this case, the upper four bits of the acknowledge
response are undefined — they hold the same values as the upper four bits of the previously issued
command.
5.
The 5th byte is compared to the contents of address 0x0000_0474 in the flash memory; the 6th byte is
compared to the contents of address 0x0000_0475 in the flash memory; likewise, the 16th byte is
compared to the contents of address 0x0000_047F in the flash memory. If the password checking fails,
the RAM Transfer routine sets the password error flag.
The 2nd byte, transmitted from the target board to the controller, is an acknowledge response to the
The 3rd byte, which the target board receives from the controller, is a command. The code for the
The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the
The 5th to 16th bytes, which the target board receives from the controller, are a 12-byte password.
• UART mode
• I/O Interface mode
If the SIO0 can be programmed to the baud rate at which the 1st byte was transferred, the boot
program programs the SC0BRCR and sends back 86H to the controller as an acknowledge. If
the SIO0 is not programmable at that baud rate, the boot program simply aborts with no error
indication.
Following the 1st byte, the controller should allow for a time-out period of five seconds. If it
does not receive 86H within the allowed time-out period, the controller should give up the
communication.
The boot program sets the RXE bit in the SC0MOD0 register to enable reception before
loading the SIO transmit buffer with 86H.
The boot program programs the SC0MOD0 and SC0CR registers to configure the SIO0 in I/O
Interface mode (clocked by the rising edge of SCLK0), writes 30H to the SC0BUF. Then, the
SIO0 waits for the SCLK0 signal to come from the controller. Following the transmission of
the 1st byte, the controller should send the SCLK clock to the target board after a certain idle
time (several microseconds). This must be done at 1/16 the desire baud rate. If the 2nd byte,
which is from the target board to the controller, is 30H, then the controller should take it as a
go-ahead. The controller must then deliver the 3rd byte to the target board at a rate equal to the
desired baud rate. The boot program sets the RXE bit in the SC0MOD0 register to enable
reception before loading the SIO transmit buffer with 30H.
TMP19A44 (rev1.3)24-21
TMP19A44
2010-04-01