tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 360

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.2.2 Serial Clock Generation Circuit
14.2.3 Receive Counter
14.2.4 Receive Control Unit
14.2.5 Receive Buffer
Serial Channel (SIO)
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This circuit generates basic transmit and receive clocks.
The receive buffer is of a dual structure to prevent overrun errors. The first receive buffer (a shift
register) stores the received data bit-by-bit. When a complete set of bits have been stored, they are
moved to the second receive buffer (SC0BUF). At the same time, the receive buffer full flag
(SC0MOD2 "RBFLL") is set to "1" to indicate that valid data is stored in the second receive buffer.
However, if the receive FIFO is set enabled, the receive data is moved to the receive FIFO and this flag
is immediately cleared.
If the receive FIFO has been disabled (SCOFCNF <CNFG> = 0 and <FDPX1:0> =01), the INTRX0
interrupt is generated at the same time. If the receive FIFO has been enabled (SCNFCNF <CNFG> = 1
and <FDPX1:0> = 01/11), an interrupt will be generated according to the SC0RFC <RIL1:0> setting.
I/O interface mode:
Asynchronous (UART) mode:
I/O interface mode:
Asynchronous (UART) mode:
In the SCLK output mode with the SC0CR <IOC> serial control register set to "0," the output
of the previously mentioned baud rate generator is divided by 2 to generate the basic clock.
In the SCLK input mode with SC0CR <IOC> set to "1," rising and falling edges are detected
according to the SC0CR <SCLKS> setting to generate the basic clock.
According to the settings of the serial control mode register SC0MOD0 <SC1:0>, either the
clock from the baud rate register, the system clock (f
TMRB2 timer, or the external clock (SCLKO pin) is selected to generate the basic clock,
SIOCLK.
The receive counter is a 4-bit binary counter used in the asynchronous (UART) mode and is
up-counted by SIOCLK. Sixteen SIOCLK clock pulses are used in receiving a single data bit
while the data symbol is sampled at the seventh, eighth, and ninth pulses. From these three
samples, majority logic is applied to decide the received data.
In the SCLK output mode with SC0CR <IOC> set to "0," the RXD0 pin is sampled on the
rising edge of the shift clock output to the SCLK0 pin.
In the SCLK input mode with SC0CR <IOC> set to "1," the serial receive data RXD0 pin is
sampled on the rising or falling edge of SCLK input depending on the SC0CR <SCLKS>
setting.
The receive control unit has a start bit detection circuit, which is used to initiate receive
operation when a normal start bit is detected.
TMP19A44(rev1.3) 14-8
SYS
/2), the internal output signal of the
TMP19A44
2010-04-01