tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 406

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Parity Control Circuit
Error Flag
Serial Channel (HSIO)
If the parity addition bit <PE> of the serial control register HC0CR is set to "1," data is sent with the
parity bit. Note that the parity bit may be used only in the 7- or 8-bit UART mode. The <EVEN> bit of
HC0CR selects either even or odd parity.
Upon data transmission, the parity control circuit automatically generates the parity with the data
written to the send buffer (HSC0BUF). After data transmission is complete, the parity bit will be stored
in HSC0BUF bit 7 <TB7> in the 7-bit UART mode and in bit 7 <TB8> in the serial mode control
register SC0MOD in the 8-bit UART mode. The <PE> and <EVEN> settings must be completed before
data is written to the send buffer.
Upon data reception, the parity bit for the received data is automatically generated while the data is
shifted to receive buffer 1 and moved to receive buffer 2 (HSC0BUF). In the 7-bit UART mode, the
parity generated is compared with the parity stored in HSC0BUF <RB7>, while in the 8-bit UART
mode, it is compared with the bit 7 <RB8> of the HC0CR register. If there is any difference, a parity
error occurs and the <PERR> flag of the HC0CR register is set.
In the I/O interface mode, the HC0CR <PERR> flag functions as an under-run error flag, not as a parity
flag.
Three error flags are provided to increase the reliability of received data.
1.
2.
Overrun error <OERR>: Bit 4 of the serial control register HC0CR
In both UART and I/O interface modes, this bit is set to "1" when an error is generated by
completing the reception of the next frame receive data before the receive buffer has been
read. If the receive FIFO is enabled, the received data is automatically moved to the receive
FIFO and no overrun error will be generated until the receive FIFO is full (or until the usable
bytes are fully occupied). This flag is set to "0" when it is read. In the I/O interface HSCLK
output mode, no overrun error is generated and therefore, this flag is inoperative and the
operation is undefined.
Parity error/under-run error <PERR>: Bit 3 of the HC0CR register
In the UART mode, this bit is set to "1" when a parity error is generated. A parity error is
generated when the parity generated from the received data is different from the parity
received. This flag is set to "0" when it is read.
In the I/O interface mode, this bit indicates an under-run error. When the double buffer control
bit <WBUF> of the serial mode control register HC0MOD2 is set to "1" in the HSCLK input
mode, if no data is set to the transmit double buffer before the next data transfer clock after
completing the transmission from the transmit shift register, this error flag is set to "1"
indicating an under-run error. If the transmit FIFO is enabled, any data content in the transmit
FIFO will be moved to the buffer. When the transmit FIFO and the double buffer are both
empty, an under-run error will be generated. Because no under-run errors can be generated in
the HSCLK output mode, this flag is inoperative and the operation is undefined. If send buffer
2 is disabled, the under-run flag <PERR> will not be set. This flag is set to "0" when it is read.
TMP19A44(rev1.3) 15-16
TMP19A44
2010-04-01