tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 43

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

The standby mode selection Status<RP > of CP0 is selected by the combination.
Please do not execute the WAIT instruction in the setting of "X" in the following table.
Clock/Standby Control
5.7 Standby Controller
5.7.1 Standby Mode
backup mode, set the RP bit in the CPO status register, and then execute the WAIT instruction.
STBYCR0<STBY2:0>.
5.7.1.1
RESERVED
STOP
SLEEP
IDLE
BACKUP STOP
BACKUP SLEEP
(Note 2)
(Note 1)
The TX19A/ H1 core has several low-consumption modes. To shift to the STOP, SLEEP, IDLE (Halt or Doze) or
Before shifting to the mode, you need to select the standby mode at the system control register
The features of the IDLE, SLEEP, STOP and backup modes are described below.
register for operation in the IDLE mode in the register of each module. This enables operation
settings for the IDLE mode. When the internal I/O has been set not to operate in the IDLE
mode, it stops operation and holds the state when the system enters the IDLE mode.
Only the CPU is stopped in this mode. The internal I/O has one bit of the ON/OFF setting
standby mode. In this mode, the TX19A/ H1 processor core stops the processer operation while
holding the status of the pipeline. The TX19A/ H1 can respond to the bus control authority request
given from the outside of the processor core.
SLEEP: Only the internal low-speed oscillator, the clock timer, the 2-phase pulse input counter and the
STOP: All the internal circuits are brought to a stop.
WAIT command and shifting to the standby mode. In this mode, the TX19A/ H1 processor core
stops the processer operation while holding the status of the pipeline. The TX19A/H1 gives no
response to the bus control authority request from the internal DMA, so the bus control authority is
maintained in this mode.
IDLE Mode
The Halt mode is activated by setting the RP bit in the status register to "0," executing the
The Doze mode is activated by setting the RP bit in the status register to "1" and shifting to the
KWUP (dynamic pull-up circuit) operate.
Table 5.3 Internal I/O setting registers for the IDLE mode
A/D converter A~C
OTHER
STBY
Internal I/O
I2C/SIO(SBI)
001
010
011
101
110
TMRB0~11
2:0
HSIO0~3
SIO0~3
TMRC
TMP19A44(rev1.3) 5-14
WDT
BACKUP STOP
BACKUP SLEEP
IDLE Mode Setting Register
SLEEP
STOP
HALT
RP=0
HALT
X
HSCxMOD1<I2Sx>
WDMOD<I2WDT>
SCxMOD1<I2Sx>
TBxRUN<I2TBx>
SBIBR1<I2SBIx>
ADMOD1<I2AD>
TCCR<I2TBT>
DOZE
DOZE
RP=1
X
X
X
X
X
TMP19A44
2010-04-01