tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 653

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Electrical Characteristics
Note :
No.
(1) DVCC3＝
27.6.2 Multiplex Bus mode
10
11
12
13
14
15
16
17
18 D0-D15
19
20
21
1
2
3
4
5
6
7
8
9
negated
ALE: Number of ALE insertion
System clock period (x)
A0-A15 VALID TO ALE LOW
A0-A15 HOLD AFTER ALE LOW
ALE pulse width high
ALE low to
asserted
A0-A15 valid to
A16-A23 valid to
asserted
A16-A23 hold after
negated
A0-A15 valid to D0-D15 Data in
A16-A23 valid to D0-D15 Data in
D0-D15 hold after
WR
D0-D15 valid to
negated
A16-A23 valid to
A0-A15 valid to
RD
RD
RD
RD
W: Number of Auto wait insertion
N : Number of external wait insertion
WAIT
BUSCR<ALESEL>
BxxCS<BxW>
BxxCS<BxCSCV>
BxxCS<BxRCV>
BxxCS<BxWCV>
/ HWR
,
WR
negated to next A0-A15 output
asserted to D0-D15 data in
width low
hold after
or
hold
AC measurement conditions:
HWR
RD
Output levels:
Input levels:
RD
AVCC3n=
Parameter
width low
RD
,
after
,
WAIT
WR
WR
,
negated to ALE high
RD
WR
WAIT
WR
RD
RD
or
,
or
,
or
WR
input
or
negated
HWR
WR
WR
input
HWR
HWR
HWR
2.7Vto3.6V,Ta =－20to85°C
or
or
or
asserted
asserted
HWR
HWR
HWR
High = 0.8DVCC3 V/Low 0.2DVCC3 V, CL = 30 pF
High = 0.7DVCC3 V/Low 0.3DVCC3 V
=“01”
=“001”
=“01”
=“01”
=“0_1010”
TMP19A44 (rev1.3) 27-13
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYS
AL
LA
LL
LC
CL
ACL
ACH
CAR
ADL
ADH
RD
RR
HR
RAE
WW
DW
WD
AWH
AWL
CW
,
x
x (1 + ALE) – 19
x – 12
x (1 + ALE) – 6
x – 12
x(1+CSR+RWR) – 19
x (1 + ALE) − 19
x (1 + ALE) − 19
x (1＋CSR) − 19
x (1 + W) − 13
0
x(1+CSR+ RWR) -19
x (1 + W) − 13
x (1 + W) − 19
x (1 + CSR) - 19
x (W – 2) – 10
Min
Equation
x (2 + ALE + W) − 46
x (2 + ALE + W) − 46
x (1 + W) − 46
x (W – 2 + N) - 46
x (1 + ALE + W - 2) - 46
x (1 + ALE + W - 2) - 46
Max
124.5
124.5
118.5
TMP19A44
12.5
18.5
31.5
18.5
18.5
18.5
18.5
Min
0.5
0.5
(fsys)(Note)
90
6
0
6
40 MHz
Max
91.5
91.5
91.5
129
129
104
2010-04-01
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns