tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 414

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Serial Channel (HSIO)
HSC0MOD2
15.3.1.6
<TBEMP>:
<RBFLL>:
<TXRUN>:
<SBLEN>:
<DRCHG>:
<WBUF>:
<SWRST1:0>:
bit Symbol
Read/Write
After reset
Mode Control Register 2
Function
This is a flag to show that the receive double buffers are full. When a receive operation is
completed and received data is moved from the receive shift register to the receive double
buffers, this bit changes to "1" while reading this bit changes it to "0."
<TXRUN> and <TBEMP> show the following status.
decision is made using only a single bit regardless of the <SBLEN> setting.
to fix it to LSB first.
output/input modes) and receive (in HSCLK output mode) data in the I/O interface mode and
to transmit data in the UART. In all other modes, double buffering is enabled when receiving
data in I/O interface mode (HSCLK input) and UART mode regardless of the <WBUF>
setting.
If double buffering is disabled, this flag is insignificant.
This flag shows that the send double buffers are empty. When data in the send double buffers
is moved to the send shift register and the double buffers are empty, this bit is set to "1."
Writing data again to the double buffers sets this bit to "0."
If double buffering is disabled, this flag is insignificant.
This is a status flag to show that data transmission is in progress.
This specifies the length of stop bit transmission in the UART mode. On the receive side, the
Specifies the direction of data transfer in the I/O interface mode. In the UART mode, you need
This parameter enables or disables the send/receive buffers to send (in both HSCLK
Overwriting "01" in place of "10" generates a software reset.
When this software reset is executed, the following bits and their internal circuits are
initialized.
(Note 1, 2 and 3)
<TXRUN>
Register name
HSECMOD2
1
0
HSC0MOD0
HSC0MOD1
1: Empty
Send
buffer
empty flag
0: full
TBEMP
HC0CR
1
7
<TBEMP>
1: full
Receive
buffer full
flag
0: Empty
‐
RBFLL
TMP19A44(rev1.3) 15-24
1
0
R
6
0
RXE
TXE
TBEMP,RBFLL,TXRUN,
OERR,PERR,FERR
1: Start
In
transmissi
on flag
0: Stop
Transmission in progress
Transmission completed
Wait state for transmission with next data in a send
buffer.
TXRUN
5
0
Bit
1: 2-bit
Stop bit
(for UART)
0: 1-bit
SBLEN
4
0
1: MSB
Setting
transfer
direction
0: LSB
DRCHG
first
first
Status
3
0
1: Enable
W-buffer
0: Disable
WBUF
R/W
2
0
TMP19A44
Soft reset
Overwrite "01" on "10"
to reset
SWRST1
1
0
2010-04-01
SWRST0
0
0