tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 250

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

External Bus Interface
When read/write recovery is inserted (ALE width:1fsys)
fsys
A[23:16]
AD[15:0]
/RD,/WR
ALE
/CS
(4) Read and Write Recovery Time
If access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time.
A dummy cycle can be inserted in both a read and a write cycle. The dummy cycle insertion setting can be
made in the chip selector and wait controller registers, BmnCS<BnWCV> (write recovery cycle) and
<BnRCV> (read recovery cycle). As for the number of dummy cycles, none, one, two or four system
clocks (internal) can be specified for each block. Fig. 8.17 shows the timing of recovery time insertion.
Lower-order address
Normal cycle
tsys
Higher-order address
Data
Fig. 8.17 Timing of Recovery Time Insertion
Lower-order address
TMP19A44 (rev1.3) 8-22
1 recovery cycle
Higher-order address
Data
Dummy cycle
Lower-order address
Higher-order address
2 recovery cycles
TMP19A44
Data
Dummy cycle
2010-04-01